PowerQUICC® Processor with CPM (1 SCC, 2 SMC), 10/100 Ethernet

  • This page contains information on a product that is not recommended for new designs.

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Block Diagram



  • 4-Kbyte Instruction Cache
  • 4-Kbyte Data Cache
  • 8 Kb Dual Port RAM
  • Instruction and Data MMUs
  • Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8, 16, and 32 Bits)
  • 32 Address Lines
  • Complete Static Design (0-80 MHz Operation)
  • Memory Controller (Eight Banks)
  • General-Purpose Timers
  • System Integration Unit (SIU)
  • Interrupts
  • Communications Processor Module (CPM)
  • Four Baud Rate Generators
  • One SCC (Serial Communication Controller)
  • Two SMCs (Serial Management Channels)
  • One SPI (Serial Peripheral Interface)
  • One I2C (Inter-Integrated Circuit) Port
  • Time-Slot Assigner
  • Parallel Interface Port
  • PCMCIA Interface
  • Low Power Support
  • Debug Interface
  • 3.3 V Operation with 3.3V I/O

Part numbers include: MPC855TCVR50D4, MPC855TCVR66D4, MPC855TCZQ50D4, MPC855TCZQ66D4, MPC855TVR50D4, MPC855TVR66D4, MPC855TVR80D4, MPC855TZQ50D4, MPC855TZQ66D4, MPC855TZQ80D4.

Comparison Table

MPC855T Versions and Masks

Qual Process Mask IMMR [16:31]
Rev D.4 XC .32µ TLM 3K20A 0x0502
Rev D.3 XC .32µ TLM 2K20A 0x0501


Quick reference to our documentation types.

1-5 of 38 documents

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Quick reference to our board types.

3 hardware offerings


Quick reference to our software types.

1 software file

Note: For better experience, software downloads are recommended on desktop.


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