PowerQUICC® Processor with CPM (1 SCC, 2 SMC), 10/100 Ethernet

Product Details

Features

  • Embedded MPC8xx core
  • Single-issue, 32-bit version of the core (compatible with the Power Architecture definition) with 32, 32-bit general-purpose registers (GPRs)
  • The MPC859T provides enhanced ATM functionality over that of the MPC860SAR. The MPC859T adds major new features available in "enhanced SAR" (ESAR) mode, including the following:
    • Multiple APC priority levels available to support a range of traffic pace requirements
    • Port-to-port switching capability without the need for RAM-based microcode
    • Simultaneous MII (100Base-T) and UTOPIA (half-duplex) capability
    • Parameter RAM for both SPI and I2C can be relocated without RAM-based microcode
    • Supports full-duplex UTOPIA leader (ATM side) operation using a "split" bus
  • Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
  • 32 address lines
  • Complete static design
  • Memory controller (eight banks)
  • General-purpose timers
  • Fast Ethernet controller (FEC)
  • System integration unit (SIU)
  • Interrupts
  • Communications processor module (CPM)
  • On-chip 16 x 16 multiply accumulate controller (MAC)
  • Four baud rate generators
  • One SCC (serial communication controller)
  • Two SMCs (serial management channels)
  • One SPI (serial peripheral interface)
  • One I2C (inter-integrated circuit) port
  • Time-slot assigner (TSA)
  • Parallel interface port (PIP)
  • PCMCIA interface
  • Low power support
  • Debug interface
  • 3.3 V operation
  • 357-pin PBGA package

Comparison Table

MPC866 Family Versions and Masks

Qual Process Mask IMMR [16:31]
Rev 0.3 MC HiP6W 3L90H 0x0800
Rev A.0 MC HiP6W 0L96R 0x0801
Note 1: Where nn = 50, 66, 100, or 133

Documentation

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Design Resources

Hardware

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Software

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