Microcontrollers for Optimized Radar

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Block Diagram

S32R37 Block Diagram

S32R37 Block Diagram



  • Dual issue computation cores: Power Architecture® e200z7 32-bit CPU
  • 1.2 MB on-chip code flash memory (FMC flash memory) with ECC
  • 1 MB on-chip SRAM with ECC

RADAR processing

  • Signal Processing Toolbox (SPT) for RADAR signal processing acceleration
  • Cross Triggering Engine (CTE) for precise timing generation and triggering
  • MIPICSI2 interface to connect external RADAR RX ADCs

Memory protection

  • Each core memory protection unit provides 24 entries
  • Data and instruction bus system memory protection unit (SMPU) with 16 region descriptors each
  • Register protection

Functional safety

  • Enables ASIL-B applications
  • Fault Collection and Control Unit (FCCU) for fault collection and fault handling
  • Memory Error Management Unit (MEMU) for memory error management
  • Safe eDMA controller
  • Self-Test Control Unit (STCU2)
  • Error Injection Module (EIM)
  • On-chip voltage monitoring
  • Clock Monitor Unit (CMU)


  • Cryptographic Security Engine (CSE2)
  • Supports censorship and life-cycle management

SafeAssure Functional Safety Program

SafeAssure Functional Safety Program

When it comes to functional safety, NXP stands for quality and reliability. Our SafeAssure program simplifies system-level safety requirements in accordance with ISO 26262.
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