40-Bit I2C-Bus I/O Port with RESET, OE and INT

PCA9505_06

Product Details

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Block Diagram

PCA9505DGG, PCA9506BS, PCA9506DGG

Features

Key Features

  • Standard mode (100 kHz) and fast mode (400 kHz) compatible I2C-bus serial interface
  • 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os
  • 40 configurable I/O pins that default to inputs at power-up
  • PCA9505 includes 100 kΩ internal pull-up resistors on all the I/Os
  • Active LOW reset (RESET) input pin resets device to power-up default state
  • 3 programmable address pins allowing 8 devices on the same bus
  • Low standby current
  • -40 °C to +85 °C operation
  • ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC standard JESD78, which exceeds 100 mA
  • Offered in TSSOP56 (PCA9505, PCA9506) and HVQFN56 (PCA9506) packages

Outputs

  • Totem-pole (10 mA source, 15 mA sink) with controlled edge rate output structure
  • Active LOW output enable (OE) input pin 3-states all outputs
  • Output state change on acknowledge
  • Open-drain active LOW interrupt (INT) output pin allows monitoring of logic level change of pins programmed as inputs

Inputs

  • Programmable interrupt mask control for input pins that do not require an interrupt when their states change
  • Polarity inversion register allows inversion of the polarity of the I/O pins when read

Designed for Live Insertion

  • Minimize line disturbance (IOFF and power-up 3-state)
  • Signal transient rejection (50 ns noise filter and robust I2C-bus state machine)

Part numbers include: PCA9505DGG, PCA9506BS, PCA9506DGG.

Documentation

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Design Resources

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