40-Bit Fm+ I2C-Bus Advanced I/O Port with RESET, OE and INT

Block Diagram

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PCA9698 Block Diagram

PCA9698 Block Diagram

PCA9698BS, PCA9698DGG Block Diagram


Key Features

  • 1 MHz fast-mode plus I2C-bus serial interface
  • Compliant with I2C-bus fast-mode (400 kHz) and standard-mode (100 kHz)
  • 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os
  • 40 configurable I/O pins that default to inputs at power-up
  • Active LOW SMBus alert (SMBALERT) output pin allows to initiate SMBus 'alert response address' sequence. Own target address sent when sequence initiated
  • Active LOW reset (RESET) input pin resets device to power-up default state
  • GPIO all call address allows programming of more than one device at the same time with the same parameters
  • 64 programmable target addresses using 3 address pins
  • Readable device ID (manufacturer, device type and revision)
  • Designed for live insertion in PICMG applications
  • Low standby current
  • -40 °C to +85 °C operation
  • ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
  • Packages offered: TSSOP56 and HVQFN56


  • Open-drain active LOW Interrupt (INT) output pin allows monitoring of logic level change of pins programmed as inputs
  • Programmable interrupt mask control for input pins that do not require an interrupt when their states change
  • Polarity inverter register allows inversion of the polarity of the I/O pins when read

PICMG Applications

  • Minimize line disturbance (IOFF and power-up 3-state)
  • Signal transient rejection (50 ns noise filter and robust I²C-bus state machine)

Part numbers include: PCA9698BS, PCA9698DGG.


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