40-Bit Fm+ I²C-bus Advanced I/O Port with RESET, OE and INT

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Block Diagram

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PCA9698 Block Diagram

PCA9698 Block Diagram

Block diagram: PCA9698BS, PCA9698DGG

Features

  • 1 MHz Fast-mode Plus I²C-bus serial interface
  • Compliant with I²C-bus Fast-mode (400 kHz) and Standard-mode (100 kHz)
  • 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os
  • 40 configurable I/O pins that default to inputs at power-up
  • Outputs:
    • Programmable totem-pole (10 mA source, 25 mA sink) or open-drain (25 mA sink) with controlled edge rate output structure. Default to totem-pole on power-up.
    • Active LOW Output Enable (OE) input pin 3-states all outputs. Polarity can be programmed to active HIGH through the I²C-bus. Defaults to OE on power-up.
    • Output state change programmable on the Acknowledge or the STOP Command to update outputs byte-by-byte or all at the same time respectively. Defaults to Acknowledge on power-up.
  • Inputs:
    • Open-drain active LOW Interrupt (INT) output pin allows monitoring of logic level change of pins programmed as inputs
    • Programmable Interrupt Mask Control for input pins that do not require an interrupt when their states change
    • Polarity Inverter register allows inversion of the polarity of the I/O pins when read
  • Active LOW SMBus Alert (SMBALERT) output pin allows to initiate SMBus 'Alert Response Address' sequence. Own target address sent when sequence initiated.
  • Active LOW Reset (RESET) input pin resets device to power-up default state
  • GPIO All Call address allows programming of more than one device at the same time with the same parameters
  • 64 programmable target addresses using 3 address pins
  • Readable Device ID (manufacturer, device type and revision)
  • Designed for live insertion in PICMG applications
    • Minimize line disturbance (IOFF and power-up 3-state)
    • Signal transient rejection (50 ns noise filter and robust I²C-bus state machine)
  • Low standby current
  • -40 Cel to +85 Cel operation
  • ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
  • Packages offered: TSSOP56, and HVQFN56

Target Applications

  • Servers
  • RAID systems
  • Industrial control
  • Medical equipment
  • PLCs
  • Cell phones
  • Gaming machines
  • Instrumentation and test measurement

Documentation

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Design Resources

Design Files

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