16-Bit I²C-Bus and SMBus, Level Translating, Low Voltage GPIO with Reset and Interrupt

Block Diagram


PCA9575 Block Diagram


Key Features

  • Separate supply rails for core logic and each of the two I/O banks provides voltage level shifting
  • 1.1 V to 3.6 V operation with level shifting feature
  • Very low standby current: < 2 μA
  • 16 configurable I/O pins organized as 2 banks that default to inputs at power-up
  • 400 kHz I2C-bus serial interface
  • Compliant with I2C-bus Standard-mode (100 kHz)
  • Active LOW reset (RESET) input pin resets device to power-up default state
  • GPIO All Call address allows programming of more than one device at the same time with the same parameters
  • 16 programmable target addresses using 4 address pins (28-pin TSSOP only)
  • -40 °C to +85 °C operation
  • ESD protection exceeds 6000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
  • Packages offered: TSSOP28, TSSOP24, HWQFN24


  • Totem pole: 1 mA source and 3 mA sink
  • Independently programmable 100 kΩ pull-up or pull-down for each I/O pin
  • Open-drain active LOW interrupt (INT) output pin allows monitoring of logic level change of pins programmed as inputs


  • Programmable bus hold provides valid logic level when inputs are not actively driven
  • Programmable Interrupt Mask Control for input pins that do not require an interrupt when their states change or to prevent spurious interrupts default to mask at power-up
  • Polarity Inversion register allows inversion of the polarity of the I/O pins when read

Part numbers include: PCA9575HF, PCA9575PW1, PCA9575PW2.


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Design Files

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3 hardware offerings

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