8-Bit I²C-Bus and SMBus I/O Port with Reset

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Block Diagram

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PCA9557 Block Diagram

PCA9557 Block Diagram

Block diagram: PCA9557BS, PCA9557D, PCA9557PW

Block diagram: PCA9557BS, PCA9557D, PCA9557PW

Features

  • Lower voltage, higher performance migration path for the PCA9556
  • 8 general purpose input/output expander/collector
  • Input/output configuration register
  • Active HIGH polarity inversion register
  • I²C-bus and SMBus interface logic
  • Internal power-on reset
  • Noise filter on SCL/SDA inputs
  • Active LOW reset input
  • 3 address pins allowing up to 8 devices on the I²C-bus/SMBus
  • High-impedance open-drain on IO0
  • No glitch on power-up
  • Power-up with all channels configured as inputs
  • Low standby current
  • Operating power supply voltage range of 2.3 V to 5.5 V
  • 5 V tolerant inputs/outputs
  • 0 kHz to 400 kHz clock frequency
  • ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
  • Three packages offered: SO16, TSSOP16, HVQFN16

Documentation

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Design Resources

Design Files

5 design files

Hardware

1 hardware offering

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