8-bit LCD for Battery-Powered and Handheld LC MCUs

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Block Diagram

S08LC Microcontroller Block Diagram

S08LC Microcontroller Block Diagram


S08 Central Processor Unit (CPU)

  • 40 MHz (20 MHz bus) at >2.1V operation for 50 ns minimum instruction time
  • 16 MHz (8 MHz bus) frequency at <2.1V

LCD Driver and Internal Charge Pump

  • Integrated LCD driver supports both standard 3V and 5V LCD glass
  • Configurable display for 4 x 40 or 3 x 41segment display
  • Automatic blink and refresh
  • Internal charge pump
  • Capable of running in STOP3 mode

Flash Memory

  • In-application re-programmability
  • Dual flash block for enhanced EEPROM emulation

Clock Source Options

  • Internal clock generator (ICG)
  • frequency-locked loop (FLL)
  • controlled by internal or external reference

Serial Communication Ports

  • Serial communications interface (SCI) module offering asynchronous communications
  • Serial peripheral interface (SPI) module
    • Full-duplex, 3-wire synchronous transfer
    • Maximum bit rate of 5 MHz for 10 MHz bus frequency
  • Inter-integrated Circuit (I2C) bus module
    • 2-wire synchronous serial module to connect to standard I2C bus
    • Designed to operate up to 100 kbps with maximum bus loading and timing

Keyboard Interrupts (KBI) and I/O

  • Up to 16 KBI with software selectable polarity on edge or edge/level modes

Analog Integration

  • 8-channel, 12-bit ADC
  • Automatic compare function, software programmable for greater than, equal to or less than conditions
  • Temperature sensor
  • Internal bandgap reference channel
  • Trigger conversion using the real-time interrupt (RTI) counter
  • Analog comparator module
    • Option to compare to internal reference
    • Output can be optionally routed to timer / pulse width modulation module (TPM) as input capture trigger


  • Programmable 16-bit TPM
  • Each channel can be independentlyprogrammed for:
    • Input capture
    • Output compare
    • Buffered, edge-aligned pulse width modulation (PWM)
    • Buffered center-aligned PWM

System Security Features

  • Watchdog computer operating properly reset with option to run from dedicated 1 kHz internal clock source or from bus clock
  • Low-voltage detection (LVD) generates reset, interrupt or flag with two software selectable trip points
  • Low-voltage warning sets flag, with higher trip points than LVD


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Design Resources


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Note: For better experience, software downloads are recommended on desktop.

Engineering Services

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