KV5x: Kinetis^® KV5x-240 MHz, Motor Control and Power Conversion, Ethernet, MCUs based on Arm^® Cortex^®-M7

Overview

The Kinetis^® KV5x family of MCU is a high-performance solution offering exceptional precision, sensing and control targeting industrial motor control, industrial drives and automation and power conversion applications. The Kinetis KV5x MCU is built on the Arm^® Cortex^®-M7 core running at 240 MHz with single precision floating point unit. It features high-resolution pulse-width modulation (PWM) with 260 picosecond resolution, 4x 12-bit analog-to-digital converters (ADCs) sampling at 5 mega samples per second (MS/s), 3 FlexCAN modules, optional Ethernet communications and comprehensive enablement suite from NXP^® and third-party resources including reference designs, software libraries and motor configuration tools.

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Features

High-performance 240 MHz Arm^® Cortex^®-M7 core combined with a high level of analog and digital integration targeted at real-time control applications
Up to 1 MB Flash and 256 KB RAM, 16 KB instruction cache and 8 KB data cache. 256 KB of RAM includes 64 KB of ITCM RAM ensuring maximum CPU performance of fast control loops with minimal latency
64-bit AXI memory interface with I-Cache and D-Cache – efficient access to external resources; interface to large external memories for a complete RTOS experience; support for richer HMI with higher resolution graphics, multiple connectivity stacks and middleware
4 x 8ch 12-bit ADC’s sampling at 5 MSPS with a dual sample and hold circuitry, can capture current and voltage simultaneously for two motors giving true independent dual motor control
Ethernet option with True Random Number Generator and Cryptographic unit providing a low cost integrated connectivity solution
2 eFlexPWM blocks provide 4 independent time bases per module with a highly flexible configuration that easily supports motor and power control topologies
Multiple instantiations of timer blocks provide a vast array of timers (44 channels) simplifying the complex task of advanced motor control
A single eFlexPWM block featuring 12 channels with Nano-Edge capability, providing up to 260pSec resolution on pulse width and frequency modulation
Up to 3 FlexCAN modules—High speed, high-reliability industrial communication
Inter-peripheral cross-bar, with And or Invert Logic, provides a highly flexible connection fabric between peripherals that supports simplified control topology implementation

MoreLess

Features

High-performance 240 MHz Arm^® Cortex^®-M7 core combined with a high level of analog and digital integration targeted at real-time control applications
Up to 1 MB Flash and 256 KB RAM, 16 KB instruction cache and 8 KB data cache. 256 KB of RAM includes 64 KB of ITCM RAM ensuring maximum CPU performance of fast control loops with minimal latency
64-bit AXI memory interface with I-Cache and D-Cache – efficient access to external resources; interface to large external memories for a complete RTOS experience; support for richer HMI with higher resolution graphics, multiple connectivity stacks and middleware
4 x 8ch 12-bit ADC’s sampling at 5 MSPS with a dual sample and hold circuitry, can capture current and voltage simultaneously for two motors giving true independent dual motor control
Ethernet option with True Random Number Generator and Cryptographic unit providing a low cost integrated connectivity solution
2 eFlexPWM blocks provide 4 independent time bases per module with a highly flexible configuration that easily supports motor and power control topologies
Multiple instantiations of timer blocks provide a vast array of timers (44 channels) simplifying the complex task of advanced motor control
A single eFlexPWM block featuring 12 channels with Nano-Edge capability, providing up to 260pSec resolution on pulse width and frequency modulation
Up to 3 FlexCAN modules—High speed, high-reliability industrial communication
Inter-peripheral cross-bar, with And or Invert Logic, provides a highly flexible connection fabric between peripherals that supports simplified control topology implementation