Layerscape® Access LA12xx Programmable Baseband Processor

  • Preproduction
  • This page contains information on a preproduction product. Specifications and information herein are subject to change without notice. For additional information contact support or your sales representative.

Product Details

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Block Diagram

Layerscape Access LA12xx Block Diagram

Layerscape Access LA1200 Block Diagram


Core and Memory complex

  • 6x e200 32-bit CPUs
  • RF Management/control
  • Timing, frame structure control
  • 4-8x VSPA3-16@ < 640 MHz (=1.3 TFLOP)
  • Floating point SIMD compute, 32 CMAC HP /clock
  • 2 MB on-chip SRAM

Connectivity and I/O

  • 2x PCIe gen3 up to 8 lanes total
  • 2x {I+Q} 4 GSP/s ADC/DAC complex
  • Dual channel, < 1 GHz RF channel b/w mmWave bands
  • 2-4x {I+Q} 425 MSP/s ADC/850 MSPS DAC complex
  • Dual channel, < 200 MHz RF channel b/w < 7 GHz bands


  • Forward Error Correction: LDPC (5G/3GPP, gNB/UE)
  • Forward Error Correction: Polar (5G/3GPP, gNB/UE)
  • Forward Error Correction: LDPC (802.11ad/ay)

Low speed I/O and RFIC control

  • Low-speed SPI/JTAG/UART/I2C
  • Fast RFIC management through LVDS interface
  • On-chip PLL, timebase / frame timer generator


Quick reference to our documentation types.

2 documents

Design Resources


1 hardware offering


1 software file

Note: For better experience, software downloads are recommended on desktop.

Engineering Services

4 engineering services

To find a complete list of our partners that support this product, please see our Partner Marketplace.


1 trainings


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