Layerscape® 1021A Dual-Core Processor with LCD Controller
Overview
Features
Features
Core Complex
- Dual Arm v7 Cortex®-A7 32-bit cores, each supporting dual precision floating point and NEON SIMD module running up to 1.2 GHz
- 32 KB instruction and data L1 cache with single bit error detection and correction, ECC protection on both instruction and data caches
- Up to 512 KB coherent L2 cache with single bit error detection and correction, ECC protection
Networking Elements
- SerDes 4 lanes at up to 6 GHz
- Supports SGMII, PCIe® and SATA
- Ethernet
- Three virtualized enhanced triple-speed Ethernet controllers (VeTSEC) supporting SGMII (up to 2), RGMII, RMII, MII
- Support IEEE® 1588
- Twin PCIe Gen2 controllers
- Supporting up to 5G/tps in 1-lane, 2-lane, or 4-lane (with a single controller)
- MSI supported
- Four FlexCAN controllers
Accelerators and Memory Control
- DDR memory controller supports DDR3L and DDR4 at up to 1600 MHz
- 8-bit, 16-bit, 32-bit memory supported, with ECC support
- Security Engine (SEC5.4) features five cryptographic hardware acceleration modules, true random number generator, hashing and CRC unit
Basic Peripherals and Interconnect
- Arm Cache Coherent Interconnect (CCI400)
- Arm AMBA 4 MPCore Virtualization
- Integrated Flash controller supporting 16-bit interface
- QuadSPI Flash controller
- USB3.0 superspeed controller with integrated PHY, supporting OTG, Host and Device modes
- USB2.0 controller supporting OTG, Host and Device modes
- SD/MMC controller
- SATA3 controller supporting 6G/tps
- 3x I²C
- 2x SPI
Additional Features
- LCD display controller
NXP LS1021A Processor Block Diagram
NXP Priority Support: Helping You to Get to Market Faster
LS1 Family and IoT Synergy at ArmTeck - Interview
Introducing the LS1 Processor Family
LS1 Family for Networking Applications
LS1 Family for Industrial Applications
oMG Mobile Gateway (oMG) Demo at IoT Tour
From Simply Smart to Truly Intelligent: Edge Computing with i.MX and Layerscape Processors Enables Future Technology
-
NXP LS1021A Processor Block Diagram -
NXP Priority Support: Helping You to Get to Market Faster -
LS1 Family and IoT Synergy at ArmTeck - Interview -
Introducing the LS1 Processor Family -
LS1 Family for Networking Applications -
LS1 Family for Industrial Applications -
oMG Mobile Gateway (oMG) Demo at IoT Tour -
From Simply Smart to Truly Intelligent: Edge Computing with i.MX and Layerscape Processors Enables Future Technology
LS1021A Processor Block Diagram
Development Boards and Designs
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Target Applications
Communication Infrastructure
- Broadband Modem and Residential Gateway
- Enterprise Access Point
- Industrial Gateway
- IoT Gateway
- M2M Gateway
Industrial
Smart Home
- Personal/Consumer NAS
Technologies
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We recommend the following Power Management IC for LS1021A Processors
Select the specifications below to find the perfect fit for your design
| PMIC Part Number | Description | External Memory Voltage (V) | Ambient Operating Temperature (Min-Max) (°C) | Qualification Tier |
|---|---|---|---|---|
| MC34VR500V1ES | Regulator, Buck, Quad with up to 4.5A Output and Triple User-programmable LDOs, QFN 56 | 1.35 | -40 to 105 | Industrial |
| MC34VR500V2ES | Regulator, Buck, Quad with up to 4.5A Output and Factory programmed LDOs, QFN 56 | 1.35 | -40 to 105 | Industrial |