Layerscape 2084A and 2044A Multicore Processors

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Product Details

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Block Diagram

LS2084A Processor Block Diagram

LS2084A Processor Block Diagram

Features

Core Complex

  • Eight 64-bit Arm Cortex-A72 CPUs
    • Up to 2 GHz,
    • Clusters of two cores sharing 1 MB L2 cache
  • 1 MB L3 platform cache
  • Two 64-bit DDR4 SDRAM memory controllers
    • ECC and interleaving support,
    • Up to 2.1 GT/s

Networking Elements

  • Wire Rate I/O processor, featuring:
    • 8x 10 GbE
    • 8x 1 GbE
    • L2 switching on the Ethernet interface
    • XAUI/XFI/KR and SGMII
    • MACSec on up to four 1/10 GbE
  • 2x SATA 3.0
  • 4x PCIe Gen 3 controllers
  • SR-IOV support, Root Complex

Accelerators and Memory Control

  • 20 Gb/s SEC crypto acceleration
  • 10 Gb/s Pattern Matching Engine
  • 20 Gb/s Data Compression Engine
  • 4 PCIe controllers (Gen3) supporting 1x8, 4x4, 4x2, 4x1 lane configurations

Basic Peripherals and Interconnect

  • Support for hardware virtualization and partitioning enforcement
  • Implements trust architecture combined with TrustZone®
    • Service processor (SP) provides pre-boot initialization and secure-boot capabilities
  • 2x USB 3.0 with PHY
  • Enhanced secure digital host controller
  • Serial peripheral interface (SPI) controller
  • Quad Serial peripheral interface (QSPI) controller
  • Four I2C controllers
  • Two DUARTs
  • Integrated flash controller (IFC 2.0) supporting NAND and NOR flash

Documentation

Quick reference to our documentation types.

1-5 of 22 documents

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Design Resources

Hardware

4 hardware offerings

Software

3 software files

Note: For better experience, software downloads are recommended on desktop.

Engineering Services

1-5 of 8 engineering services

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Training

4 trainings

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