Low-Power PowerQUICC® II Pro Processor with DDR2, eSDHC, 128-ch. HDLC/TDM, 10/100 Ethernet, USB, IEEE® 1588

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Block Diagram

Freescale PowerQUIICC MPC8309 Communications Processor Block Diagram

NXP<sup>&#174;</sup> PowerQUIICC MPC8309 Communications Processor Block Diagram


  • e300 core running up to 417 MHz, DDR2 @ 266 MHz
  • QUICC Engine® running up to 200 MHz
  • 2 x HDLC/TDM
  • 3 x 10/100 or 2 x 10/100 w/IEEE1588v2
  • USB 2.0
  • eSDHC (boot from eSDHC support)
  • 4 x CAN
  • 4 x UART
  • 32-bit PCI Interface
  • Local bus (boot from NOR/NAND flash memory support)
  • 1.03W typical at 333 MHz e300 core/200 MHz QUICC Engine (maximum = 1.37W)
  • 489-pin, 19 mm x 19 mm MAPBGA package
  • This product is included in NXP®.s product longevity program, with assured supply for a minimum of 10 years.


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Design Resources

Design Files

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  • Models

    MPC8309 BSDL Model


4 hardware offerings


3 software files

Note: For better experience, software downloads are recommended on desktop.

Engineering Services

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To find a complete list of our partners that support this product, please see our Partner Marketplace.


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