Integrated Host Processor with DDR, PCI, RapidIO® and 1G Ethernet

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Block Diagram

Freescale PowerQUIICC MPC8540 Communications Processor Block Diagram

NXP<sup>&#174;</sup> PowerQUIICC MPC8540 Communications Processor Block Diagram

Features

  • Embedded e500 compatible core available from 600 MHz up to 1 GHz
  • 32-bit, dual-issue, superscalar, seven-stage pipeline
  • 1850 MIPS at 800 MHz (est. Dhrystone 2.1)
  • 32 KB L1 data and 32 KB L1 instruction cache with line locking support
  • 256 KB on-chip L2 cache with direct mapped capability
  • Enhanced hardware and software debug support
  • Memory management unit (MMU)
  • SIMD extension with single precision floating point
  • Two triple-speed Ethernet controllers (TSECs) supporting 10/100/1000 Mbps Ethernet (IEEE® 802.3, 802.3u, 802.3x, 802.3z, and 802.3ac compliant) with two GMII/TBI/RGMII interfaces
  • 166 MHz, 64-bit, 2.5-volt I/O, DDR SDRAM memory controller with full ECC support
  • 500 MHz, 8-bit, LVDS I/O, RapidIO controller
  • 133 MHz, 64-bit, 3.3-volt I/O, PCI-X 1.0a/PCI 2.2 bus controller
  • 166 MHz, 32-bit, 3.3-volt I/O, local bus with memory controller
  • 10/100 Ethernet controller (802.3) for chip debug and maintenance support
  • Integrated four-channel DMA controller
  • Interrupt controller
  • IEEE 1149.1 JTAG test access port
  • 1.2-volt core power supply with 3.3-volt and 2.5-volt I/O
  • 783-pin FC-BGA package
  • This product is included in NXP®.s product longevity program, with assured supply for a minimum of 10 years after launch
  • Design Resources

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    Software

    4 software files

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