PowerQUICC® III Processor with DDR2, PCI, PCI Express®, SerDes, 1 GB Ethernet, SGMII, Security

  • MPC8544 device is "Not recommended for new designs", please use the replacement families Power Architecture (T1013, T1023), \n Arm Architecture (LS1012A, LS1023A).

Block Diagram

NXP PowerQUICC MPC8544E Communications Processor Block Diagram

PowerQUICC<sup>&#174;</sup> MPC8544E Communications Processor Block Diagram

Features

  • Embedded e500 core, initial offerings from 667 MHz up to 1.067 GHz
    • Dual dispatch superscalar, 7-stage pipeline design with out-of-order issue and execution
    • 2,240 MIPS at 1.0 GHz (estimated Dhrystone 2.1)
    • 36-bit physical addressing
  • Integrated L1/L2 cache
    • L1 cache—32 KB data and 32 KB instruction cache with line-locking support
    • L2 cache—256 KB (8-way set associative); 256/128/64/32 KB can be used as SRAM
    • L1 and L2 hardware coherency
    • L2 cache and I/O transactions can be stashed into L2 cache regions
  • Integrated DDR memory controller with full ECC support, offering:
    • 200 MHz clock rate (400 MHz data rate), 64-bit, 2.5V/2.6V I/O, DDR SDRAM
    • 267 MHz clock rate (up to 533 MHz data rate), 64-bit, 1.8V I/O, DDR2 SDRAM
  • Integrated security engine supporting DES, 3DES, MD-5, SHA-1/2, AES, RSA, RNG, Kasumi F8/F9 and ARC-4 encryption algorithms (MPC8544E)
  • Two on-chip enhanced triple speed Ethernet controllers (ETSECs) supporting 10 Mbps, 100 Mbps and 1 Gbps Ethernet/IEEE® 802.3 networks with MII, RMII, GMII, RGMII TBI and RTBI physical interfaces as well as SGMII interfaces through a dedicated SerDes.
    • TCP/UDP/IP checksum acceleration
    • Advanced QoS features
  • Enhanced hardware and software debug support
  • Double-precision embedded scalar and vector floating-point APUs
  • Memory management unit (MMU)
  • PCI Express high-speed interconnect interfaces, supporting combinations of dual x4 and single x1 PCI Express
  • On-chip network switch fabric
  • PCI interface support
    • 32-bit PCI 2.2 bus controller (up to 66 MHz, 3.3V I/O)
  • Local bus
    • 133 MHz, 32-bit, 3.3V I/O, local bus with memory controller
  • Integrated four-channel DMA controller
  • Dual I²C and DUART support
  • Programmable interrupt controller (PIC)
  • IEEE 1149.1 JTAG test access port
  • 1.0V core voltage with 3.3V and 2.5V I/O
  • 783-pin FC-PBGA package
  • Operating junction temperature range: TJ = 0º to +105ºC, Extended temperature range: TJ = -40º to +105ºC
  • This product is included in NXP®.s product longevity program, with assured supply for a minimum of 10 years after launch
  • Part numbers include: MPC8544CVJALFA, MPC8544CVJANGA, MPC8544CVJAQGA, MPC8544ECVJALFA, MPC8544ECVJANGA, MPC8544ECVJAQGA, MPC8544EVJALFA, MPC8544EVJANGA, MPC8544EVJAQGA, MPC8544EVJARJA, MPC8544EVTANGA, MPC8544EVTAQGA, MPC8544EVTARJA, MPC8544VJALFA, MPC8544VJANGA, MPC8544VJAQGA, MPC8544VJARJA, MPC8544VTALFA, MPC8544VTAQGA, MPC8544VTARJA.

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