QorIQ® T1024

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The QorIQ^® dual-core T1024 and T1023 and single-core T1014 and T1013 communications processors combine 64-bit cores, built on Power Architecture^® technology, with high-performance Data Path Acceleration Architecture (DPAA) and network peripheral bus interfaces required networking, telecommunications and industrial networked applications. The QorIQ T Series platform offers optimized features for the industrial market, including a display interface unit for HMI, the QUICC Engine^® for industrial protocol offload and ECC support for high reliability “always on” applications.

The T1024 and T1014 processors come in a full-featured 23x23 mm package, which provides scalable, pin compatibility with the quad-core T1042 processor, and even the eight core T2081 processor for price and power scaling with a single system design.

The QorIQ T1023 and T1013 communications processors are interface and power-optimized SoCs designed to deliver impressive single- or dual-core performance for cost and power sensitive networking and industrial systems. Both versions offer an excellent software compatible 64-bit and I/O upgrade path for the popular QorIQ P10XX family of 32-bit communications processors.

Data Sheet

Reference Manual

Product Details

Block Diagram

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31538 T1023 BD
31538 T1024 BD

31538 T1023 BD

QorIQ T1013 and T1023 Communications Processors

31538 T1024 BD

QorIQ T1014 and T1024 Communications Processors

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Features

Core Complex

Single and dual e5500 cores, built on Power Architecture technology
Up to 1.4 GHz with 64-bit ISA support
Three levels of instructions: user, supervisor, hypervisor
Hybrid 32-bit mode to support legacy software and transition to a 64-bit architecture
256 KB backside L2 cache

Networking Elements

SerDes
- Four lanes at up to 10 Gbps
- Supports SGMII, QSGMII, PCIe and SATA
Ethernet Interfaces
- 1x 10GbE and 3x 1GbE or 4x 1Gbe Gigabit Ethernet interfaces, with MACsec on all ports

Accelerators and Memory Control

32/64-bit DDR3L/4 SDRAM memory controller with ECC support
- Up to 1600 MT/s
DPAA incorporating acceleration for the following functions: packet parsing, classification and distribution
- Queue management for scheduling, packet sequencing and congestion management
- Hardware buffer management for buffer allocation and de-allocation
- Integrated security acceleration (SEC)

Basic Peripherals and Interconnect

CoreNet^{^®} platform cache
- 256 KB shared platform cache
Hierarchical interconnect fabric
- CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet endpoints
Additional peripheral interfaces one Serial ATA (SATA 2.0) controllers
- Two high-speed USB 2.0 controllers with integrated PHYs
- Enhanced secure digital host controller (SD/MMC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Two I²C controllers
- Four UARTS
- Integrated flash controller supporting NAND and NOR flash
DMA
- Dual four channel
- Up to 4.1 Gbps Ethernet MACs as part of DPAA
QUICC Engine^®
- Support for legacy protocols TDM, HDLC, UART and ISDN
High-speed peripheral interfaces
- Three PCI Express^® 2.0 controllers

Additional Features

Support for hardware virtualization and partitioning enforcement
- Extra privileged level for hypervisor support
QorIQ^{^®} trust architecture
- Secure boot, secure debug, tamper detection, volatile key storage
This product is included in Our product longevity program, with assured supply for a minimum of 10 years after launch

We recommend the following Quad Port Gigabit Copper EEE PHY

Product Detail

	F104S8A	F104X8A
Description	QSGMII PHY Standard Temperature	QSGMII PHY Extended Temperature
Operating Temperature (°C)	0 - 125	-40 - 125
Package Type	12x12, QFN, 138-pin, 0.65mm pin pitch	12x12, QFN, 138-pin, 0.65mm pin pitch
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Documentation

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1-5 of 26 documents

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^{Fact Sheet}
QorIQ^® T1024/14 and T1023/13 Communications Processors - Fact SheetFeatured

PDFRev 2Nov 4, 2015139.0 KBT1024FSEnglish, 中文
^{Data Sheet}
QorIQ T1024, T1014 Data Sheet

PDFRev 1Dec 21, 20163.3 MBT1024English
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^{Data Sheet}
QorIQ T1023, T1013 Data Sheet

PDFRev 1Dec 21, 20162.9 MBT1023English
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^{Reference Manual}
QorIQ T1024 Reference Manual

PDFRev 1Sep 5, 201821.4 MBT1024RMEnglish
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^{Reference Manual}
QUICC Engine Block Reference Manual with Protocol Interworking - Reference Manual

PDFRev 9May 3, 201813.4 MBQEIWRMEnglish
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^{Reference Manual}
e5500RM, e5500 Core Reference Manual with Updates - Reference Manual

PDFRev 4Jul 28, 20153.7 MBE5500RMEnglish
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^{Reference Manual}
T1024DPAArm, QorIQ T1024 Data Path Acceleration Architecture (DPAA) Reference Manual

PDFRev 0Jul 24, 201516.2 MBT1024DPAARMEnglish
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^{Reference Manual}
T1024SECRM, QorIQ^® T1024 Security (SEC) Reference Manual - Reference Manual

PDFRev 0Jul 24, 20158.0 MBT1024SECRMEnglish
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^{Application Note}
Thermal Management Unit Usage

PDFRev 0Apr 27, 2022241.6 KBAN12310English
^{Application Note}
PBL Configuration using QCVS Application Note

PDFRev 1Nov 30, 20201.0 MBAN5260English, 中文
^{Application Note}
AN5097, Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces - Application Note

PDFRev 2Jul 10, 20191.5 MBAN5097English
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^{Application Note}
AN4971, QorIQ T1024 Family Design Checklist - Application Note

PDFRev 3May 18, 2018648.1 KBAN4971English
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^{Application Note}
U-Boot Bring Up using CodeWarrior on T1040D4RDB Application Note

PDFRev 0Apr 9, 201810.9 MBAN12105English
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^{Application Note}
AN4829, Common Board Design Between T1024 and T1022 Processor - Application Note

PDFRev 0Jul 24, 2017401.1 KBAN4829English
^{Application Note}
AN5079, QorIQ P1 Series to T1 Series Migration Guide - Application Note

PDFRev 0Jul 24, 2017349.9 KBAN5079English
^{Application Note}
SerDes Configuration and Validation Tool Companion Application Note

PDFRev 2Jan 29, 2016426.5 KBAN5119English
^{Application Note}
AN5125, Introduction to Device Trees - Application Note

PDFRev 0Sep 3, 2015566.4 KBAN5125English
^{Application Note}
AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes

PDFRev 0Jan 21, 20141.2 MBAN4848English
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^{Application Note}
AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note

PDFRev 6Nov 25, 2013547.7 KBAN3940English
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^{Application Note}
SerDes Reference Clock Interfacing and HSSI Measurements Recommendations

PDFRev Rev. 0May 13, 2011577.2 KBAN4311English
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^{Application Note}
DDR Interleaving for PowerQUICC and QorIQ Processors

PDFRev 1Jun 30, 2010717.3 KBAN3939English
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^{Product Brief}
T1024/14 and T1023/13 - Product Brief

PDFRev 0Apr 5, 2015199.8 KBT1024PBEnglish
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^{Supporting Information}
FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP^® Cryptographic Accelerators - White Paper

PDFRev 1.9Oct 28, 2016303.5 KBFSLNISTCAVPEnglish
^{Supporting Information}
T1014_13 Family Customer Export Control Information

PDFRev 1Oct 5, 201618.5 KBT1014_13-PECIEnglish
^{Supporting Information}
T1024_23 Family Customer Export Control Information

PDFRev 1Oct 5, 201618.5 KBT1024_23-PECIEnglish
^{White Paper}
QORIQPMWP, QorIQ Power Management - White Paper

PDFRev 0Mar 30, 20171.4 MBQORIQPMWPEnglish

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Design Resources

Hardware

4 hardware offerings

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^{Evaluation and Development Boards}
QorIQ^® T1024 Development BoardFeatured

T1024RDB
^{Evaluation and Development Boards}
QorIQ^® T1023 Development BoardFeatured

T1023-RDB
^{Emulators, Probes, and Programmers}
CodeWarrior^® TAP

CW_TAP
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^Designs
T1023 WLAN Access Point System

RDT1023WLAN

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