QorIQ® T2080 and T2081 Multicore Communications Processors

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Product Details

Block Diagram

T2080 BD IMG

QorIQ T2080 Communication Processor

Features

Core Complex

  • Four dual-threaded e6500 cores built on Power Architecture® technology
    • Up to 1.8 GHz each, 6.0 DMIPS/MHz per core
    • Shares a 2 MB L2 cache
    • Three levels of instructions: User, supervisor, hypervisor
    • Hybrid 32-bit mode to support legacy software and transition to a 64-bit architecture
    • Advanced power management saving modes include state retention during power gating

Basic Peripherals and Interconnect

  • CoreNet® platform cache
  • Hierarchical interconnect fabric
    • CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet endpoints
  • Additional peripheral interfaces
    • Two high-speed USB 2.0 controllers with integrated PHYs
    • Enhanced secure digital host controller (SD/MMC/eMMC)
    • Enhanced serial peripheral interface (eSPI)
    • Four I²C controllers
    • Four UARTS
    • Integrated flash controller supporting NAND and NOR flash memory

Accelerators and Memory Controller

  • 64-bit DDR3/3L SDRAM memory controller with ECC support
    • Up to 2.1 GT/s
    • Memory pre-fetch engine
  • DPAA incorporating acceleration for the following functions
    • Packet parsing, classification and distribution up to 24Gb/s (FMAN)
    • Queue management for scheduling, packet sequencing and congestion management of up to 2^24 queues (QMAN)
    • Hardware buffer management for buffer allocation and de-allocation with 64 buffer pools (BMAN)
    • Integrated security acceleration (SEC) to 10 Gbps
    • Decompression/compression acceleration at up to 17.5 Gbps (DCE)
    • Signature detection (PME) to 10Gb/s
    • DPAA support of RapidIO® messaging (RMAN) (T2080 only)

Networking Elements

  • SerDes
    • 8 lanes at up to 10GHz
    • 8 lanes at up to 8GHz (T2080 only)
  • Ethernet interfaces: 8 MACS (7 on T2081) multiplexed over the following options
    • Up to four 10 Gb/s MACs supporting XFI/KR, XAUI, and HiGig (two on T2081 supporting XFI/KR only)
    • Up to eight SGMII (5 on T2080)
    • Up to four 2.5Gb/s SGMII
    • Up to two RGMII
  • High-speed peripheral interfaces
    • Two PCI Express 3.0 controllers (one on T2081)
    • Two PCI Express 2.0 controllers (three on T2081)
    • Endpoint SR-IOV
    • Two Serial RapidIO 2.1 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support (T2080 only)
    • Two Serial ATA (SATA) 2.0 controllers (T2080 only)
  • DMA
    • Dual eight channel

Additional Features

  • Support for hardware virtualization and partitioning enforcement
    • Extra privileged level for hypervisor support
    • Logical to real address translation
    • Virtual core aware MMU/TLB
    • vMPIC (virtualized interrupt controller)/virtual core capable PPC cores
    • vDMA (user level DMA engine)
    • PAMUv2 (I/O MMU supporting paging)
    • DPAA (Ethernet MAC virtualization, accelerator virtualization)
  • Trust architecture secure boot
    • Secure boot, secure debug, tamper detection, volatile key storage, alternate image and key revocation
  • This product is included in our product longevity program, with assured supply for a minimum of 10 years after launch

Comparison Table

T2080 T2081
SerDes168
PCIe2x Gen3 + 2x Gen21x Gen3 + 3x Gen2
SRIO2 + RManNo
SATA2No
AuroraYesNo
10Gbps MACsUp to 4, with XFI, XAUI, and HiGigUp to 2 with XFI
1 Gbps MACsUp to 8Up to 7
Package25 x 25 mm , 896 pins, 0.8mm pitch23 x 23 mm, 780 pins, 0.8mm pitch, pin compatible with T1042

Documentation

Quick reference to our documentation types.

1-5 of 29 documents

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Design Resources

Hardware

4 hardware offerings

Software

4 software files

Note: For better experience, software downloads are recommended on desktop.

Engineering Services

1-5 of 18 engineering services

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To find a complete list of our partners that support this product, please see our Partner Marketplace.

Training

3 trainings

Support

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