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QorIQ^® T1040 and T1020 Multicore Communications Processors

Overview

The QorIQ^® T1040 quad-core and the T1020 dual-core communication processors support two or four integrated 64-bit e5500 Power Architecture^® processor cores with high-performance data path acceleration architecture (DPAA) and network peripheral interfaces required for networking and telecommunications.

The T1040 and T1020 are the industry’s first 64-bit embedded processors with an integrated gigabit Ethernet switch. The T family is ideally suited for use in mixed control and data plane applications such as fixed routers, switches, integrated access devices, firewall and other packet filtering applications, as well as general-purpose embedded computing. Its high level of integration offers significant performance benefits and greatly helps to simplify hardware and software design.

The T1 family of devices is one of the industry’s most scalable, pin-compatible family of communications processors – and offers pin-compatible migration up to the higher-performance QorIQ T2081 device.

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Features

Core Complex

Two or four e5500 cores, built on Power Architecture technology
Up to 1.4 GHz with 64-bit ISA support
Three levels of instructions: user, supervisor, hypervisor
Hybrid 32-bit mode to support legacy software and transition to a 64-bit architecture
256 KB backside L2 cache

Networking Elements

SerDes
- Eight lanes at up to 5 Gbps
- Supports SGMII, QSGMII, PCIe and SATA
Ethernet Interfaces
- Eight-port Gigabit Ethernet switch

Accelerators and Memory Control

32/64-bit DDR3L/4 SDRAM memory controller with ECC support
- Up to 1600 MT/s
DPAA Incorporating acceleration for the following functions Packet parsing, classification, and distribution
- Queue management for scheduling, packet sequencing and congestion management
- Hardware buffer management for buffer allocation and de-allocation
- Integrated security acceleration (SEC)
- Signature detection (PME)
- Up to five Gigabit Ethernet Interfaces

Basic Peripherals and Interconnect

CoreNet^® platform cache
- 256 KB shared platform cache
Hierarchical interconnect fabric
- CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet endpoints
Additional peripheral interfaces two Serial ATA (SATA 2.0) controllers
- Two high-speed USB 2.0 controllers with integrated PHYs
- Enhanced secure digital host controller (SD/MMC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Two I²C controllers
- Four UARTS
- Integrated flash controller supporting NAND and NOR flash
DMA
- Dual four channel
- Up to 5x 1 Gbps Ethernet MACs as part of DPAA
QUICC Engine^®
- Support for legacy protocols TDM, HDLC, UART and ISDN
High-speed peripheral interfaces
- Four PCI Express^® 2.0 controllers

Additional Features

Support for hardware virtualization and partitioning enforcement
- Extra privileged level for hypervisor support
QorIQ^® trust architecture
- Secure boot, secure debug, tamper detection, volatile key storage
This product is included in our product longevity program, with assured supply for a minimum of 10 years after launch

MoreLess

Features

Core Complex

Two or four e5500 cores, built on Power Architecture technology
Up to 1.4 GHz with 64-bit ISA support
Three levels of instructions: user, supervisor, hypervisor
Hybrid 32-bit mode to support legacy software and transition to a 64-bit architecture
256 KB backside L2 cache

Networking Elements

SerDes
- Eight lanes at up to 5 Gbps
- Supports SGMII, QSGMII, PCIe and SATA
Ethernet Interfaces
- Eight-port Gigabit Ethernet switch

Accelerators and Memory Control

32/64-bit DDR3L/4 SDRAM memory controller with ECC support
- Up to 1600 MT/s
DPAA Incorporating acceleration for the following functions Packet parsing, classification, and distribution
- Queue management for scheduling, packet sequencing and congestion management
- Hardware buffer management for buffer allocation and de-allocation
- Integrated security acceleration (SEC)
- Signature detection (PME)
- Up to five Gigabit Ethernet Interfaces

Basic Peripherals and Interconnect

CoreNet^® platform cache
- 256 KB shared platform cache
Hierarchical interconnect fabric
- CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet endpoints
Additional peripheral interfaces two Serial ATA (SATA 2.0) controllers
- Two high-speed USB 2.0 controllers with integrated PHYs
- Enhanced secure digital host controller (SD/MMC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Two I²C controllers
- Four UARTS
- Integrated flash controller supporting NAND and NOR flash
DMA
- Dual four channel
- Up to 5x 1 Gbps Ethernet MACs as part of DPAA
QUICC Engine^®
- Support for legacy protocols TDM, HDLC, UART and ISDN
High-speed peripheral interfaces
- Four PCI Express^® 2.0 controllers

Additional Features

Support for hardware virtualization and partitioning enforcement
- Extra privileged level for hypervisor support
QorIQ^® trust architecture
- Secure boot, secure debug, tamper detection, volatile key storage
This product is included in our product longevity program, with assured supply for a minimum of 10 years after launch

Data Sheets

Application Notes

Buy

QorIQ T1040/20 and T1042/22 Communication Processors

NXP Priority Support: Helping You to Get to Market Faster

QorIQ^® T1 Family - Introduction

QorIQ<sup>®</sup> T1 Family - Introduction thumbnail

QorIQ T1040/20 and T1042/22 Communication Processors
NXP Priority Support: Helping You to Get to Market Faster
QorIQ^® T1 Family - Introduction

QorIQ T1040/20 and T1042/22 Communication Processors

NXP Priority Support: Helping You to Get to Market Faster

QorIQ^® T1 Family - Introduction

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Development Boards and Designs

T1040RDB : QorIQ<sup>®</sup> T1040 Reference Design Board thumbnail

T1040RDB:QorIQ^® T1040 Reference Design Board

Evaluation and Development Boards

Development Boards and Designs

T1040RDB:QorIQ^® T1040 Reference Design Board

Evaluation and Development Boards

Target Applications

Automotive

Communication Infrastructure

Industrial

Smart City

POS Terminal

Smart Home

Technologies

Comparison Table

	T1020	T1022	T1040	T1042	T2081
CPU	2 e5500	2 e5500	4 e5500	4 e5500	4 e6500 (dual-threaded)
Core Frequency	1200-1400MHz	1200-1400MHz	1200-1400MHz	1200-1400MHz	1500-1800MHz
DDR I/F	1x DDR3L/4 to 1600MT/s	1x DDR3L/4 to 1600MT/s	1x DDR3L/4 to 1600MT/s	1x DDR3L/4 to 1600MT/s	1x DDR3/3L to 2133MT/s
Ethernet (with IEEE1588v2)	8-Port GE Switch + 4x 1GE	5x 1GE	8-Port GE Switch + 4x 1GE	5x 1GE	2x 1/10GE + 6x 1GE
SERDES	8 lanes (5GHz)	8 lanes (5GHz)	8 lanes (5GHz)	8 lanes (5GHz)	8 lanes (10GHz)
Package	Pin Compatible

We recommend the following Quad Port Gigabit Copper EEE PHY

	F104S8A	F104X8A
Description	QSGMII PHY Standard Temperature	QSGMII PHY Extended Temperature
Operating Temperature (°C)	0 - 125	-40 - 125
Package Type	12x12, QFN, 138-pin, 0.65mm pin pitch	12x12, QFN, 138-pin, 0.65mm pin pitch
Read More	Product Detail