QorIQ® T1042

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The QorIQ T1042 quad-core and T1022 dual-core communication processors support two or four integrated 64-bit e5500 Power Architecture^® processor cores with high-performance data path acceleration architecture (DPAA) and network peripheral interfaces required for networking and telecommunications.

The T1 family of devices is a scalable, pin-compatible family of communications processors – and offers pin-compatible migration up to the higher-performance QorIQ T2081 device.

Data Sheet

Reference Manual

Product Details

Block Diagram

QorIQ T1040/20 and T1042/22 Communication Processors

Get diagram PDF

Features

Core Complex

Two or four e5500 cores, built on Power Architecture technology
Up to 1.4 GHz with 64-bit ISA support
Three levels of instructions: user, supervisor, hypervisor
Hybrid 32-bit mode to support legacy software and transition to a 64-bit architecture
256 KB backside L2 cache

Networking Elements

SerDes
- Eight lanes at up to 5 Gbps
- Supports SGMII, QSGMII, PCIe and SATA
Ethernet Interfaces
- Up to five Gigabit Ethernet interfaces

Accelerators and Memory Control

32/64-bit DDR3L/4 SDRAM memory controller with ECC support
- Up to 1600 MT/s
DPAA Incorporating acceleration for the following functions Packet parsing, classification, and distribution
- Queue management for scheduling, packet sequencing and congestion management
- Hardware buffer management for buffer allocation and de-allocation
- Integrated security acceleration (SEC)
- Signature detection (PME)

Basic Peripherals and Interconnect

CoreNet^{^®} platform cache
- 256 KB shared platform cache
Hierarchical interconnect fabric
- CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet endpoints
Additional peripheral interfaces two Serial ATA (SATA 2.0) controllers
- Two high-speed USB 2.0 controllers with integrated PHYs
- Enhanced secure digital host controller (SD/MMC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Two I^{2^{C controllers}}
- Four UARTS
- Integrated flash controller supporting NAND and NOR flash
DMA
- Dual four channel
- Up to 5x 1 Gbps Ethernet MACs as part of DPAA
QUICC Engine^®
- Support for legacy protocols TDM, HDLC, UART and ISDN
High-speed peripheral interfaces
- Four PCI Express^® 2.0 controllers

Additional Features

Support for hardware virtualization and partitioning enforcement
- Extra privileged level for hypervisor support
QorIQ^{^®} trust architecture
- Secure boot, secure debug, tamper detection, volatile key storage
This product is included in Our product longevity program, with assured supply for a minimum of 10 years after launch

Comparison Table

	T1020	T1022	T1040	T1042	T2081
CPU	2 e5500	2 e5500	4 e5500	4 e5500	4 e6500 (dual-threaded)
Core Frequency	1200-1400MHz	1200-1400MHz	1200-1400MHz	1200-1400MHz	1500-1800MHz
DDR I/F	1x DDR3L/4 to 1600MT/s	1x DDR3L/4 to 1600MT/s	1x DDR3L/4 to 1600MT/s	1x DDR3L/4 to 1600MT/s	1x DDR3/3L to 2133MT/s
Ethernet (with IEEE1588v2)	8-Port GE Switch + 4x 1GE	5x 1GE	8-Port GE Switch + 4x 1GE	5x 1GE	2x 1/10GE + 6x 1GE
SERDES	8 lanes (5GHz)	8 lanes (5GHz)	8 lanes (5GHz)	8 lanes (5GHz)	8 lanes (10GHz)
Package	Pin Compatible

Documentation

Quick reference to our documentation types.

1-5 of 23 documents

^{Fact Sheet}
QorIQ T Series T1020/22 and T1040/42 Processors - Fact SheetFeatured

PDFRev 2Feb 14, 2017289.7 KBT1FAMILYFSEnglish, 中文
^{Data Sheet}
QorIQ^® T1042, T1022 Data Sheet

PDFRev 2Jun 29, 20151.5 MBT1042English
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^{Reference Manual}
QorIQ T1040 Reference Manual

PDFRev 2Jun 5, 202021.2 MBT1040RMEnglish
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^{Reference Manual}
QUICC Engine Block Reference Manual with Protocol Interworking - Reference Manual

PDFRev 9May 3, 201813.4 MBQEIWRMEnglish
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^{Reference Manual}
e5500RM, e5500 Core Reference Manual with Updates - Reference Manual

PDFRev 4Jul 28, 20153.7 MBE5500RMEnglish
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^{Reference Manual}
T1040DPAArm, T1040 QorIQ Data Path Acceleration Architecture (DPAA) Reference Manual - Reference Manual

PDFRev 0Feb 3, 201518.4 MBT1040DPAARMEnglish
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^{Reference Manual}
T1040SECRM, T1040 Security (SEC) Reference Manual - Reference Manual

PDFRev 0Jan 22, 201512.8 MBT1040SECRMEnglish
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^{Application Note}
Hardware and Layout Design Considerations for DDR4 SDRAM Memory Interfaces

PDFRev 3Jul 28, 20231.1 MBAN5097English
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^{Application Note}
U-Boot Bring Up using CodeWarrior on T1040D4RDB Application Note

PDFRev 0Apr 9, 201810.9 MBAN12105English
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^{Application Note}
AN4829, Common Board Design Between T1024 and T1022 Processor - Application Note

PDFRev 0Jul 24, 2017401.1 KBAN4829English
^{Application Note}
AN5079, QorIQ P1 Series to T1 Series Migration Guide - Application Note

PDFRev 0Jul 24, 2017349.9 KBAN5079English
^{Application Note}
SerDes Configuration and Validation Tool Companion Application Note

PDFRev 2Jan 29, 2016426.5 KBAN5119English
^{Application Note}
AN4825, T1040 Family Design Checklist - Application Note

PDFRev 1Apr 9, 2015862.5 KBAN4825English
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^{Application Note}
AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes

PDFRev 0Jan 21, 20141.2 MBAN4848English
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^{Application Note}
AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note

PDFRev 6Nov 25, 2013547.7 KBAN3940English
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^{Application Note}
SerDes Reference Clock Interfacing and HSSI Measurements Recommendations

PDFRev Rev. 0May 13, 2011577.2 KBAN4311English
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^{Application Note}
DDR Interleaving for PowerQUICC and QorIQ Processors

PDFRev 1Jun 30, 2010717.3 KBAN3939English
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^{Application Note}
PowerQUICC™ HDLC Support and Example Code

PDFRev 0Nov 10, 2009496.6 KBAN3966English
^{User Guide}
Spectre and Meltdown Updates for Power ISA Cores

HTMLNov 14, 2019SPECTRE-MELTDOWN-POWER-ISA-DOCEnglish
^{Product Brief}
T1040/20 and T1042/22 Product Brief

PDFRev 0Apr 2, 2014222.3 KBT1040PBEnglish
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^{Supporting Information}
FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP^® Cryptographic Accelerators - White Paper

PDFRev 1.9Oct 28, 2016303.5 KBFSLNISTCAVPEnglish
^{White Paper}
Speculative Execution Vulnerabilities and Mitigations on NXP PowerPC Processors White Paper

PDFRev 0Jan 30, 2020317.1 KBSPECTREPPCWPEnglish
^{White Paper}
QORIQPMWP, QorIQ Power Management - White Paper

PDFRev 0Mar 30, 20171.4 MBQORIQPMWPEnglish

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Design Resources

Design Files

1 design file

^Models
BDSL file for T1020/22

BSDLRev R1AFeb 20, 2019 14:25:00112.8 KBT1020-T1022-BSDL
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Download

Hardware

2 hardware offerings

^{Evaluation and Development Boards}
QorIQ^® T1040 Reference Design BoardFeatured

T1040RDB
^{Emulators, Probes, and Programmers}
CodeWarrior^® TAP

CW_TAP

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PowerTrace system provides full insights of what an embedded system is doing without impacting its real-time performance. It ensures bringing designs to market faster and...

By Lauterbach GmbH Gold Partner
^{Test Accessories and Debugger}
TRACE32® Debug and Trace tools for PowerPC-based NXP Microcontroller

TRACE32® provides a complete suite of tools for NXP's PowerPC-based Microcontrollers. They provide unparalleled levels of debug capabilities to get the best out of PowerP...

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Green Hills Probe

High speed on-chip download, run control and trace.

By Green Hills Software Platinum Partner
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PowerDebug is Lauterbach's powerful, modular, flexible debug system. It provides the broadest coverage of supported chips and core architectures in the embedded industry ...

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