32-bit MCU for Low-End Automotive Powertrain Applications

MPC5534 Active
  • This page contains information on a product that is not recommended for new designs.

The NXP® MPC5534 MCU provides an ultra-low cost solution for low-end engine management applications.

  • Supports applications requiring complex, real-time control
  • Offers system performance along with the reliability and familiarity of the proven Power Architecture®
  • Controls design costs for increasingly complex applications
  • Includes a peripheral set specifically tailored for automotive and industrial applications
  • Delivers more on-chip functionality than the current MPC500 family
  • Offers a migration path from the MPC500 family, facilitating reuse of legacy software architectures

Product Details

Block Diagram

Freescale MPC5534 Microcontroller Block Diagram

NXP<sup>&#174;</sup> MPC5534 Microcontroller Block Diagram
Get diagram PDF

Features

Our e200z3 Core + VLE

  • High-performance 80 MHz 32-bit Power Architecture core with VLE
  • Memory management unit (MMU) with 16-entry fully associative translation lookaside buffer (TLB)
  • SPE (signal processing extension): DSP, SIMD and floating point capabilities

Memory

  • 1 MB of embedded flash memory with error correction coding (ECC) and read while write capability (RWW)
  • 64 KB on-chip static RAM with ECC system

System

  • One enhanced time processor units (eTPUs) with 32 I/O channels and 14.5k of designated SRAM
  • 32-channel eDMA (enhanced direct memory access) controller
  • Interrupt controller (INTC) capable of handling 210 selectable-priority interrupt sources
  • Frequency modulated phase-locked loop (FMPLL) to assist in electromagnetic interference (EMI) management
  • MPC500 compatible external bus Interface
  • Nexus IEEE®-ISTO 5001 class 3+ multicore debug capabilities
  • 5/3.3V IO, 5V ADC, 3.3V/1.8V bus, 1.5V core
  • 208-pin MAPBGA and 324-pin PBGA package options
  • Temperature Range: -40 to 125ºC

I/O

  • 40 channel dual enhanced queued analog-to-digital converter (eQADC)—up to 12 bit resolution and up to 1.25ms conversions, six queues with triggering and DMA support
  • Three deserial serial peripheral interface (DSPI) modules-16 bits wide up to six chip selects each
  • Two controller area network (CAN) modules with 64 buffers each
  • Two enhanced serial communication interface (eSCI) modules
  • 24-channel enhanced multiple I/O system (EMIOS) with unified channels

Development Tools

  • A comprehensive suite of hardware and software development tools is available to help simplify and speed system design
  • Development support is available from leading tools vendors providing compilers, debuggers and simulation development environments

Included in NXP ®.s product longevity program

Buy/Parametrics

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