Design Files
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This part is not recommended for new designs. For new designs, we recommend UJA1163ATK.
The UJA1163 is a mini high-speed CAN System Basis Chip (SBC) containing an ISO 11898-2/5 compliant HS-CAN transceiver and an integrated 5 V/100 mA supply for a microcontroller. The UJA1163 can be operated in a very low-current Standby mode with bus wake-up capability and supports ISO 11898-6 compliant autonomous CAN biasing.
The UJA1163 implements the standard CAN physical layer as defined in the current ISO11898 standard (-2 and -5). Pending the release of the updated version of ISO11898 including CAN FD, additional timing parameters defining loop delay symmetry are included. This implementation enables reliable communication in the CAN FD fast phase at data rates up to 2 Mbit/s.
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Quick reference to our documentation types.
3 documents
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Receive the full breakdown. See the product footprint and more in the eCad file.
Receive the full breakdown. See the product footprint and more in the eCad file.
2 hardware offerings
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1 software offerings
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1 software offerings
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