LPC3131FET180: Low-cost, low-power Arm926EJ-S^™ MCUs with high-speed USB 2.0 OTG, SD/MMC, and NAND flash controller

Overview

The NXP^® LPC3130/3131 combine an 180 MHz ARM926EJ-S CPU core, high-speed USB 2.0 On-The-Go (OTG), up to 192 KB SRAM, NAND flash controller, flexible external bus interface, four channel 10-bit ADC, and a myriad of serial and parallel interfaces in a single chip targeted at consumer, industrial, medical, and communication markets. To optimize system power consumption, the LPC3130/3131 have multiple power domains and a very flexible Clock Generation Unit (CGU) that provides dynamic clock gating and scaling.

Features

CPU platform

180 MHz, 32-bit ARM926EJ-S
16 kB D-cache and 16 kB I-cache
Memory Management Unit (MMU)

Internal memory

96 kB (LPC3130) or 192 kB (LPC3131) embedded SRAM

External memory interface

NAND flash controller with 8-bit ECC
8/16-bit Multi-Port Memory Controller (MPMC): SDRAM and SRAM

Communication and connectivity

High-speed USB 2.0 (OTG, Host, Device) with on-chip PHY
Two I²S-bus interfaces
Integrated master/slave SPI
Two master/slave I²C-bus interfaces
Fast UART
Memory Card Interface (MCI): MMC/SD/SDIO/CE-ATA
Four-channel 10-bit ADC
Integrated 4/8/16-bit 6800/8080 compatible LCD interface

System functions

Dynamic clock gating and scaling
Multiple power domains
Selectable boot-up: SPI flash, NAND flash, SD/MMC cards, UART, or USB
DMA controller
Four 32-bit timers
Watchdog timer
PWM module
Random Number Generator (RNG)
General Purpose I/O (GPIO) pins
Flexible and versatile interrupt structure
JTAG interface with boundary scan and Arm^® debug access

Operating voltage and temperature

Core voltage: 1.2 V
I/O voltage: 1.8 V, 2.8 V, 3.3 V
Temperature: -40 Cel to +85 Cel

TFBGA180 package: 12 x 12 mm², 0.8 mm pitch

Features

CPU platform

180 MHz, 32-bit ARM926EJ-S
16 kB D-cache and 16 kB I-cache
Memory Management Unit (MMU)

Internal memory

96 kB (LPC3130) or 192 kB (LPC3131) embedded SRAM

External memory interface

NAND flash controller with 8-bit ECC
8/16-bit Multi-Port Memory Controller (MPMC): SDRAM and SRAM

Communication and connectivity

High-speed USB 2.0 (OTG, Host, Device) with on-chip PHY
Two I²S-bus interfaces
Integrated master/slave SPI
Two master/slave I²C-bus interfaces
Fast UART
Memory Card Interface (MCI): MMC/SD/SDIO/CE-ATA
Four-channel 10-bit ADC
Integrated 4/8/16-bit 6800/8080 compatible LCD interface

System functions

Dynamic clock gating and scaling
Multiple power domains
Selectable boot-up: SPI flash, NAND flash, SD/MMC cards, UART, or USB
DMA controller
Four 32-bit timers
Watchdog timer
PWM module
Random Number Generator (RNG)
General Purpose I/O (GPIO) pins
Flexible and versatile interrupt structure
JTAG interface with boundary scan and Arm^® debug access

Operating voltage and temperature

Core voltage: 1.2 V
I/O voltage: 1.8 V, 2.8 V, 3.3 V
Temperature: -40 Cel to +85 Cel

TFBGA180 package: 12 x 12 mm², 0.8 mm pitch

Application Notes

sot570-3_3d

sot570-3_3d

sot570-3_3d

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