Arm926EJ-S with 256 KB SRAM, USB High-Speed OTG, SD/MMC, Nand Flash Controller, Ethernet, LCD Controller

LPC3250FET296

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Product Details

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Block Diagram

Block diagram: LPC3220FET296, LPC3230FET296, LPC3240FET296, LPC3250FET296

Features

  • ARM926EJS processor, running at CPU clock speeds up to 266 MHz
  • Vector Floating Point (VFP) coprocessor
  • 32 kB instruction cache and a 32 kB data cache
  • Up to 256 kB of Internal SRAM (IRAM)
  • Selectable boot-up from various external devices
  • Multi-layer AHB system that provides a separate bus for each AHB leader
  • External memory controller for DDR and SDR SDRAM as well as for static devices
  • Two NAND flash controllers
  • Leader Interrupt Controller (MIC) and two Follower Interrupt Controllers (SIC)
  • Eight channel General Purpose DMA (GPDMA) controller on the AHB
  • 10/100 Ethernet MAC with dedicated DMA Controller
  • USB interface supporting either device, host (OHCI compliant), or On-The-Go
  • Four standard UARTs with fractional baud rate generation
  • Three additional high-speed UARTs intended for on-board communications
  • Two SPI controllers
  • Two SSP controllers
  • Two I2C-bus interfaces with standard open-drain pins
  • Two I2S-bus interfaces, each with separate input and output channels
  • LCD controller supporting both STN and TFT panels
  • Secure Digital (SD) memory card interface
  • General Purpose (GP) input, output, and I/O pins
  • 10 bit, 400 kHz Analog-to-Digital Converter (ADC)
  • Real-Time Clock (RTC) with separate power pin and dedicated 32 kHz oscillator
  • 32-bit general purpose high-speed timer with a 16-bit pre-scaler
  • Six enhanced timer/counters
  • 32-bit millisecond timer driven from the RTC clock
  • WatchDog timer clocked by the peripheral clock
  • Two single-output PWM blocks
  • Motor control PWM
  • Keyboard scanner function allows automatic scanning of an up to 8 x 8 key matrix
  • Up to 18 external interrupts
  • Standard Arm® test/debug interface for compatibility with existing tools
  • Emulation Trace Buffer (ETB) with 2048 x 24 bit RAM allows trace via JTAG
  • Stop mode saves power
  • On-chip crystal oscillator
  • An on-chip PLL allows CPU operation up to the maximum CPU rate
  • Boundary scan for simplified board testing

Target Applications

  • Consumer
  • Medical
  • Industrial
  • Network control

Documentation

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Design Resources

Design Files

4 design files

Hardware

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  • Test Accessories and Debugger

    J-Link PLUS

  • Test Accessories and Debugger

    Arm ULINKpro

  • Test Accessories and Debugger

    J-Link EDU

  • Test Accessories and Debugger

    J-Link BASE

  • Test Accessories and Debugger

    Universal Access Device 3+ (UAD

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Software

1 software file

Note: For better experience, software downloads are recommended on desktop.

Engineering Services

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Training

4 trainings

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