Ultra-Reliable MPC56xS MCU for Automotive and Industrial Instrument Clusters


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Block Diagram

MPC564xS Block Diagram

MPC564xS Block Diagram


  • Dual-issue, 32-bit Power Architecture Book E compliant CPU core complex (e200z4d) Memory management unit and 4 KB instruction cache
  • Variable length encoding (VLE) instruction set enables significant code size reduction over conventional Book E-compliant code
  • Up to 2 MB on-chip flash with flash controller
  • Separate 4 x 16 KB flash block for EEPROM emulation
  • Up to 64 KB on-chip SRAM with ECC
  • Up to 1 MB on-chip graphics SRAM (no ECC)
  • Two TFT displays up to WVGA resolution parallel data interface (PDI) for digital video input
  • Sound generation and playback using PCM or DDS sources with 4-channel mixer and PWM or I2S outputs
  • Stepper motor drivers with stepper stall detect for up to six gauges


Quick reference to our documentation types.

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Design Resources

Design Files

1 design file

  • Calculators

    MPC56xx EEPROM Emulation Endurance Calculator


4 hardware offerings


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Note: For better experience, software downloads are recommended on desktop.

Engineering Services

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To find a complete list of our partners that support this product, please see our Partner Marketplace.


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