Kinetis K81-150 MHz HW Cryptographic Co-Processor, Anti-Tamper and QuadSPI Microcontrollers (MCUs) Based on Arm® Cortex®-M4 Core

K81_150

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The Kinetis® K81 MCU extends the Kinetis MCU portfolio with advanced security capabilities including anti-tamper peripheral, boot ROM to support encrypted firmware updates, automatic decryption from external serial flash memory, AES acceleration, and hardware support for public key cryptography. The K81 MCU can be used to meet the security standards for point-of-sale (PoS) applications.

Please contact your local NXP representative to download the K81 Security Data sheet and Reference Manual documents (under NDA).

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Block Diagram

Kinetis K81_150 MCU Block Diagram

Kinetis K81_150 MCU Block Diagram
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Features

Memory and Scalability

  • 256 KB of Flash
  • 256 KB of SRAM
  • CPU cache consisting of separate 8 KB I/D and 8 KB system cache
  • QSPI controller optimized for XIP from external serial NOR flash memories with support for quad and octal data interfaces
  • SDRAM and external memory bus interfaces
  • eMMC/SDIO interface through eSDHC peripheral

Ultra Low Power

  • Flexible low-power modes with power and clock gating for optimal peripheral activity and recovery times. Stop currents of <340 nA, run currents of 200 µA/MHz, 5.8 µs wake-up from Stop mode
  • Full memory and analog operation down to 1.71 volts for extended battery life
  • Low-leakage wake-up unit with up to seven internal modules and 24 pins as wake-up sources in low-leakage stop (LLS)/very low-leakage stop (VLLS) modes
  • Low-power peripherals and DMA for continuous system operation in reduced power state

Performance

  • Arm ® Cortex ®-M4 core + DSP up to 150 MHz, single-cycle MAC, single instruction multiple data (SIMD) extensions, single precision floating point unit
  • Up to 32-channel DMA for peripheral and memory servicing with reduced CPU loading and faster system throughput
  • CPU cache consisting of separate 8 KB I/D and 8 KB system cache
  • Crossbar switch enables concurrent multi-leader bus accesses, increasing bus bandwidth

Cost Saving Integration

  • 48 MHz internal reference clock capable of supporting full-speed USB device without an external crystal
  • Integrated USB regulator to allow direct connection to 5 V from USB cables
  • Separate I/O power domain for several pins allowing interfaces without external level translators
  • Analog voltage reference provides an accurate reference to analog blocks, ADC and DAC, and replaces external voltage references to reduce system cost

HMI (Human Machine Interface)

  • 32-Pin FlexIO block capable of interfacing to camera or displays
  • External memory bus for connection to smart display modules
  • Touch Sense interface supported by Kinetis ® SDK software library
  • GPIO pins with support for digital filtering

Mixed Signal Capability

  • 16-bit analog-to-digital converter (ADC) with configurable resolution. Single or differential output mode operation for improved noise rejection
  • 12-bit digital-to-analog converters (DACs) for analog waveform generation for audio applications
  • Two high-speed comparators providing fast and accurate motor over-current protection by driving PWMs to a safe state
  • Analog voltage reference provides an accurate reference to analog blocks, ADC and DAC, and replaces external voltage references to reduce system cost

Connectivity and Communications

  • USB 2.0 On-The-Go (full-speed) with USB transceiver. Intelligent design with embedded 48 MHz oscillator allowing for USB crystal-less system design. Device charge detect optimizes charging current/time for portable USB devices enabling longer battery life. Low-voltage regulator supplies up to 120 mA off-chip at 3.3 volts to power external components from 5 volts input
  • Up to four UARTs with IrDA support
  • EMVSIM module with ISO7816 smart card support
  • Inter-IC Sound (I2S) serial interface for audio system interfacing
  • Three DSPI and four I2C

Reliability and Safety

  • Memory protection unit provides memory protection for all leaders on the crossbar switch, increasing software reliability
  • Cyclic redundancy check engine validates memory contents and communication data, increasing system reliability
  • Independent-clocked COP guards against clock skew or code runaway for fail-safe applications such as the IEC 60730 safety standard for household appliances
  • External watchdog monitor drives output pin to safe state external components if watchdog event occurs

Advanced Security

  • Flash and chip security settings
  • Memory protection unit provides memory protection for all leaders on the crossbar switch, increasing software reliability
  • Hardware implementation of security operations Symmetrical crypto. Supports DES, 3DES, AES, MD5, SHA-1 and SHA-256 algorithms
  • Ability to disable JTAG and chip unique ID
  • ROM support for encrypted firmware updates
  • Flash Access controller to create execute only regions of embedded flash
  • Hardware crypto co-processor with support for DES, AES and Public key cryptography
  • On-the-fly AES decryption and execution from external serial NOR flash
  • Tamper detect module with detection temperature, voltage, clock or pin tampers with the ability to create active tamper meshes
  • 2 KB of secure session RAM linked to the tamper detect module

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