Product Details

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Block Diagram

MPC555 Block Diagram

MPC555 Block Diagram

Features

  • 40 MHz core with floating point unit
  • 26 KB of static RAM
  • 448 KB flash EEPROM memory with 5-volt programming (CMF)
  • Flexible memory protection unit
  • GPIO support
  • Two time processor units (TPU3)
  • 18-channel modular I/O system (MIOS1)
  • Two queued analog-to-digital converter modules (QADC)
  • Two CAN 2.0B controller modules (TouCANs)
  • Queued serial multi-channel module (QSMCM)
  • U-bus system interface unit (USIU)

Documentation

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1-5 of 101 documents

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Design Resources

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Design Files

3 design files

  • Models

    IBIS models for the MPC555

  • Models

    IBIS models for the MPC555 Rev M

  • Printed Circuit Boards and Schematics

    MPC555 Evaluation Board Schematics

Hardware

1 hardware offering

Software

1 software file

Note: For better experience, software downloads are recommended on desktop.

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