32 Bit Microcontroller

MPC565

The MPC565 is a member of the MPC500 family of microprocessors that implements the Power Architecture® instruction standard architecture. The MPC565 is integrated with a floating point unit, an advanced peripheral set and 1 MB of flash memory on a single chip. This combination is ideal for high-performance automotive applications as well as other control-intensive applications.

Product Details

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Block Diagram

MPC565 Block Diagram

MPC565 Block Diagram
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Features

General

  • 1 MB of internal flash memory (divided into two blocks of 512 KB)
  • 36 KB static RAM
  • Three time processor units (TPU3)
  • A 22-timer channel modular I/O system (MIOS14)
  • Three TouCAN modules
  • Two enhanced queued analog system with analog multiplexors (AMUX) for 40 total analog channels. These modules are configured so each module can access all 40 of the analog inputs to the part
  • Two queued serial multi-channel modules, each of which contains a queued serial peripheral interface (QSPI) and two serial controller interfaces (SCI/UART)
  • A J1850 (DLCMD2) communications module
  • A NEXUS debug port (class 3) – IEEE®ISTO 5001-1999
  • JTAG and background debug mode (BDM)

Documentation

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Design Resources

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Design Files

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2 design files

  • Models

    IBIS models for the MPC565

    ZIPRev 1.0Sep 4, 2003 00:00:00203.2 KBMPC565IBISSW
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  • Printed Circuit Boards and Schematics

    MPC566EVB Evaluation Board Schematic for the MPC565/566/535/536

    ZIPRev BApr 10, 2003 00:00:001.1 MBMPC566EVB
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Hardware

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Software

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Training

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