32-bit MCU for Body Electronics Applications

Product Details

Block Diagram

MPC5510 Block Diagram

MPC5510 Block Diagram

Features

  • Power Architecture e200z1 core with variable length encoding (VLE)
  • Optional VLE-only 32/16-bit e200z0 secondary core
  • 16-channel eDMA (enhanced direct memory access)
  • Memory management unit (MMU) with 4-entry translation look-aside buffer (TLB)
  • Multiple low-power modes
  • JTAG and Nexus class 2+ debug support
  • Up to 1.5 MB of flash with error correction coding (ECC)
  • The flash module features read while write (RWW) and small partitions for optimal bootloader and EEPROM emulation support
  • Up to 80 KB of SRAM with ECC
  • Memory protection unit (MPU) with up to 16 regions and 32B granularity
  • This product is included in NXP®.s product longevity program, with assured supply for a minimum of 15 years after launch

Key Parametrics

  • Flash (kB)
    1000, 1500, 512
  • Operating Frequency [Max] (MHz)
    48, 66, 80
  • GPIO
    111, 137, 145

Design Resources

Documentation

Quick reference to our documentation types.

1-5 of 53 documents

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Design Files

2 design files

Hardware

1-5 of 6 hardware offerings

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Software

4 software files

Note: For better experience, software downloads are recommended on desktop.

Engineering Services

1-5 of 8 engineering services

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To find a complete list of our partners that support this product, please see our Partner Marketplace.

Training

1-5 of 6 trainings

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