32-bit MCU for Automotive Powertrain Applications

Product Details

Block Diagram

MPC5553 Block Diagram

MPC5553 Block Diagram

Features

Our e200z6 Core

  • High-performance 132 MHz 32-bit Power Architecture core
  • Memory management unit (MMU) with 32-entry fully associative translation lookaside buffer (TLB)
  • SPE (signal processing extension): DSP, SIMD and floating point capabilities

Memory

  • 1.5 MB of embedded flash memory with error correction coding (ECC) and read while write capability (RWW)
  • 64 KB on-chip static RAM with ECC
  • 8 KB of cache (with line-locking) that can be configured as additional RAM

System

  • An enhanced time processor unit (eTPUs) with 32 I/O channels and 14.5 KB of dedicated SRAM
  • 32-channel eDMA (enhanced direct memory access) controller
  • Interrupt controller (INTC) capable of handling 210 selectable-priority interrupt sources
  • Frequency modulated phase-locked loop (FMPLL) to assist in electromagnetic interference (EMI) management
  • MPC500 compatible external bus interface
  • Nexus IEEE®-ISTO 5001 class 3+ multicore debug capabilities > 5/3.3V IO, 5V ADC, 3.3V/1.8V bus, 1.5V core
  • Fast Ethernet connection(FEC)
  • 416-pin PBGA, 324-pin PBGA, or 208 MAPBGA package
  • Temperature range: -40 to 125ºC

I/O

  • 40-channel dual enhanced queued analog-to-digital converter (eQADC)—up to 12 bit resolution and up to 1.25us conversions, six queues with triggering and DMA support
  • Three deserial serial peripheral interface (DSPI) modules—16-bits wide up to six chip selects each
  • Two controller area network (CAN) modules with 64 buffers each
  • Two enhanced serial communication interface (eSCI) modules
  • 24-channel enhanced multiple I/O system (EMIOS) with unified channels

Development Tools

  • A comprehensive suite of hardware and software development tools is available to help simplify and speed system design
  • Development support is available from leading tools vendors providing compilers, debuggers and simulation development environments

Included in NXP product longevity program

Key Parametrics

  • Flash (kB)
    1500
  • Operating Frequency [Max] (MHz)
    112, 132, 32, 80
  • GPIO
    220

Design Resources

Documentation

Quick reference to our documentation types.

1-5 of 99 documents

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Design Files

2 design files

Hardware

1-5 of 8 hardware offerings

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Software

1-5 of 26 software files

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Note: For better experience, software downloads are recommended on desktop.

Engineering Services

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To find a complete list of our partners that support this product, please see our Partner Marketplace.

Training

1-5 of 7 trainings

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