32-bit MCU for Automotive Powertrain Applications

MPC5566

Designed for engine management, the NXP® MPC5566 embedded controller provides developers with a cost-effective medium to support more sophisticated, memory-intensive timing and control functionality.

  • Helps increase fuel efficiency and improved emissions
  • Allows more advanced engine control systems to be deployed
  • Enables easy migration to next-generation 3 MB flash-embedded controllers
  • Offers system performance of up to five times that of its MPC500 predecessors
  • Ideal for any application that requires complex, real-time control
  • Qualifies for the harshest automotive environments
  • Pin-and code-compatible with other MPC5500 family MCUs

Product Details

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Block Diagram

MPC5566 Block Diagram

MPC5566 Block Diagram
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Features

Our e200z6 Core

  • High-performance 132 MHz 32-bit Power Architecture technology core with variable length encoding (VLE)
  • Memory management unit (MMU) with 32-entry fully associative translation lookaside buffer (TLB)
  • SPE (signal processing extension): DSP, SIMD and floating point capabilities

Memory

  • 3 MB of embedded flash memory with error correction coding (ECC) and RWW
  • 128 KB on-chip static RAM with ECC
  • 32 KB of cache (with line-locking) that can be configured as additional RAM

System

  • Two enhanced time processor units (eTPUs), each with 32 I/O channels and 24 KB of designated SRAM
  • 64-channel eDMA (enhanced direct memory access) controller
  • Interrupt controller (INTC) capable of handling 339 selectable-priority interrupt sources
  • Frequency modulated phase-locked loop (FMPLL) to assist in electromagnetic interference (EMI) management
  • MPC500 compatible external bus interface
  • Nexus IEEE®-ISTO 5001 class 3+ multicore debug capabilities > 5/3.3V IO, 5V ADC, 3.3V/1.8V bus, 1.5V core
  • 416-pin PBGA package
  • Temperature range: -40 to 125ºC

I/O

  • 40-channel dual enhanced queued analog-to-digital converters (eQADC)—each up to 12 bit resolution and up to 1.25 us conversions, six queues with triggering and DMA support
  • Four deserial serial peripheral interface (DSPI) modules—16 bits wide up to six chip selects each
  • Four controller area network (CAN) modules with 64 buffers each
  • Two enhanced serial communication interface (eSCI) modules
  • 24-channel enhanced multiple I/O system (EMIOS) with unified channels

Included in NXP ®.s product longevity program

Documentation

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Design Resources

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Hardware

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Software

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1-5 of 28 software files

  • BSP, Drivers and Middleware

    MPC55XX Flash Driver

    ZIPRev 3.2.3Jan 22, 2008 00:00:005.1 MBMPC55XX_FLASH_DRIVER
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  • BSP, Drivers and Middleware

    MPC55XX EEPROM Emulation Driver

    EXERev 4.0.4Dec 17, 2012 00:00:005.4 MBMPC55XX_EEPROM_EMU_DRIVER
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  • Code Snippets

    The example presentmethods 2a and 2b from the AN2817

    TGZRev 0Mar 21, 2014 00:00:00253.5 KBMPC5566-WDT-WDT-2AB-CW210-V0-0
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  • Code Snippets

    The example receives data via ESCI_A with 9600bps in interrupt mode and send them back

    TGZRev 0Mar 21, 2014 00:00:00100.4 KBMPC5566-ESCI-ECHO-CW210-V0-0
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  • Code Snippets

    The example present method 3 from the AN2817

    TGZRev 0Mar 21, 2014 00:00:00222.4 KBMPC5566-WDT-WDT-3-CW210-V0-0
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Note: For better experience, software downloads are recommended on desktop.

Engineering Services

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To find a complete list of our partners that support this product, please see our Partner Marketplace.

Training

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