32-bit MCU for Powertrain Applications

MPC5554
  • Not Recommended for New Designs
  • This page contains information on a product that is not recommended for new designs.

The MPC5554 MCU enables complex, real-time control for engine management systems. It offers system performance of up to five times that of its MPC500 predecessors along with the reliability and familiarity of proven Power Architecture® technology.

  • Reduces costs by integrating more functionality on-chip
  • Development support speeds time-to-market
  • Supports multiple protocols and customer requirements through intelligent subsystems
  • Offers a migration path from the MPC500 MCUs, facilitating reuse of legacy software architectures

Product Details

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Block Diagram

MPC5554 Block Diagram

MPC5554 Block Diagram
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Features

Our e200z6 Core

  • High-performance 132 MHz 32-bit core built on Power Architecture technology
  • Memory management unit (MMU) with 32-entry fully associative translation lookaside buffer (TLB)
  • SPE (signal processing extension): DSP, SIMD and floating point capabilities

Memory

  • 2 MB of embedded flash memory with error correction coding (ECC) and read while write (RWW) capability
  • 64 KB on-chip static RAM with ECC
  • 32 KB of cache (with line-locking) that can be configured as additional RAM

System

  • Two enhanced time processor units (eTPUs) with 64 I/O channels and 19 KB of designated SRAM
  • 64-channel enhanced direct memory access (eDMA) controller
  • Interrupt controller (INTC) capable of handling 286 selectable-priority interrupt sources
  • Frequency modulated phase-locked loop (FMPLL) to assist in electromagnetic interference (EMI) management
  • MPC500 compatible external bus interface
  • Nexus IEEE®-ISTO 5001 class 3+ multicore debug capabilities
  • 5/3.3V IO, 5V ADC, 3.3V/1.8V bus, 1.5V core
  • 416-pin plastic ball grid array (PBGA) package
  • Temperature range: -40ºC to 125ºC
  • Optional temperature range: -55ºC to 125ºC

I/O

  • 40-channel dual enhanced queued analog-to-digital converter—up to 12-bit resolution and up to 1.25 ms conversions, six queues with triggering and DMA support
  • Four deserial serial peripheral
  • Interface (DSPI) modules—16 bits wide, up to six chip selects each
  • Three controller area network (CAN) modules with 64 buffers each
  • Two enhanced serial communication interface modules

Development Tools

  • A comprehensive suite of hardware and software development tools is available to help simplify and speed system design
  • Development support is available from leading tools vendors providing compilers, debuggers and simulation development environments

Included in NXP ®.s product longevity program

Design Resources

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