MPC8358E: PowerQUICC® II Pro Processor with DDR2, TDM, PCI, Security, USB, QUICC Engine® with 1 GB Ethernet, UTOPIA
Overview
Features
Features
DDR memory controller
- Programmable timing supporting DDR-1 and DDR-2 SDRAM
- 2 x 32-bit or 1 x 64-bit data interface; up to 266 MHz data rate
- Four banks of memory, each up to 1 GB
- Full ECC support
e300 core operating from 266 MHz to 400 MHzv
- 32-bit, high-performance superscalar core
- 756 MIPS at 400 MHz; 503 MIPS at 266 MHz
- Double-precision floating point, integer, load/store, system register branch processor units and 32 KB data and 32 KB instruction cache with line-locking support
QUICC Engine® initially operating up to 400 MHz
- Two 32-bit RISC controllers for flexible support of the communications peripherals
- Six unified communication controllers (UCCs) supporting the following protocols and interfaces:
- 10/100/1000 Mbps Ethernet
- ATM SAR supporting AAL5, AAL2, AAL1,AAL0, TM 4.0 CBR,VBR, UBR traffic types, up to 64KB external connections
- Inverse multiplexing for ATM (IMA)
- POS up to 622 Mbps
- Transparent
- HDLC
- HDLC bus
- UART
- BISYNC
Four TDM interfaces (T1/E1)
- Aggregate bandwidth of 64 kbps and 256 channels
- Maximum of 16 Mbps and 256 channels on a single TDM link
- 2,048 bytes of SI RAM (1,024 entries)
- Eight programmable strobes
- Bit or byte resolution
- Independent transmit and receive routing, frame synchronization
- Supports T1, CEPT, T1/E1, T3/E3, pulse-code modulation highway, ISDNprimary/basic rate, NXP® interchip digital link (IDL) and user-defined TDM serial interfaces PCI interface
- One 32-bit PCI 2.2 bus controller (3.3V I/O; up to 66 MHz)
PCI interface
- One 32-bit PCI 2.2 bus controller (3.3V I/O; up to 66 MHz)
Integrated security (MPC8360E and MPC8358E only)
- Public key execution (RSA and Diffie-Hellman)
- Data encryption standard execution (DES and 3DES)
- Advanced encryption standard (AES) execution
- ARC-4 execution (RC4-compatible algorithm)
- Message digest execution (SHA, MD5, HMAC)
- Random number generation (RNG)
Local bus controller
- Multiplexed 32-bit address and data operating up to 133 MHz
- 32-, 16- and 8-bit port sizes controlled by on-chip memory controller
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Target Applications
Automotive
Communication Infrastructure
Smart City
QUICC Engine Product Comparison
| MPC8358E | MPC8360E | |
|---|---|---|
| CPU | e300 | e300 |
| I-Cache/D-Cache (KB) | 32/32 | 32/32 |
| Available clock frequencies | Up to 400 MHz | Up to 667 MHz |
| QUICC Engine | 2 x RISC core | 2 x RISC core |
| Available clock frequencies | Up to 400 MHz | Up to 500 MHz |
| Ethernet | Up to 2 x 10/100/1,000 Up to 6 x 10/100 |
Up to 2 x 10/100/1,000 Up to 8x 10/100 |
| ATM | 1 x UTOPIA L2 | 2 x UTOPIA L2 |
| MPHY | Single 31/128 port | 128 per UTOPIA port |
| POS | Yes | Yes |
| TDM | Up to 4 TDM interfaces (QMC) Up to 256 channels at 16 Mbps on a single interface Up to four clear channel T3/E3 |
Up to 8 TDM interfaces (MCC) Up to 256 channels at 16 Mbps on a single interface Up to eight clear channel T3/E3 |
| Memory controller | 1 x 32/64-bit DDR | 1 x 32/64-bit or 2 x 32-bit DDR |
| Local bus | Yes | Yes |
| PCI | One 32-bit (up to 66 MHz) | One 32-bit (up to 66 MHz) |
| Integrated security engine* | Yes | Yes |
| DUART | Yes | Yes |
| I 2C controller | 2 | 2 |
| SPI | 2 | 2 |
| USB | Yes | Yes |
| Interrupt controller | Yes | Yes |
| Package options | 740 TBGA 668 PBGA |
740 TBGA |