MCX A25: Enhanced Mainstream Arm® Cortex® M33 MCU with 180 MHz for PC Accessories and Motor Control

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Block Diagram

MCX A255 and MCX A256

MCX-A255-A256-BD

Features

Core Platform

  • Arm® Cortex®-M33 180MHz

Processing Accelerators

  • SmartDMA, coprocessor for applications such as parallel camera interface and keypad scanning

Memory

  • Single-bank Flash: Up to 1024 kB Flash with ECC (supports one-bit correction and two-bit detection)
  • Cache Engine with 8 kB RAM
  • Up to 256 kB RAM of which 8 kB is shared with cache, configurable as up to 8 kB RAM with ECC (support one-bit correction and two-bit detection)
  • All RAM can be retained down to Deep Power-down mode
  • ROM

Peripherals

  • Analog
    • 2x 16-bit ADC
      • Up to 3.2 Msps in 16-bit mode, and 4 Msps in 12-bit mode
      • Up to 43 ADC Input channels total (depending on the package)
      • Integrated temperature sensor
    • 1 x 12-bit DAC
      • Up to 1 Msps
    • 2 x High-speed Comparators with 8 input pins and 8-bit DAC as internal reference
      • 1x LPCMP is functional down to Deep Power-down mode
    • 1x OPAMP without PGA
    • Advanced Motor Control
      • Up to 2x FlexPWM each with 4 submodules, providing 16 complementary outputs of PWM (no Nanoedge module)
      • Up to 2x Quadrature Encoder/Decoder (eQDC)
      • 2x AOI (AND/OR/Invert) module supports up to 4 output triggers
  • Timers
    • 5 x 32-bit standard general-purpose asynchronous timers/counters, which support up to four capture inputs and four compare outputs, PWM mode and external count input. Specific timer events can be selected to generate DMA requests
    • Low power timerer
    • Frequency measurement timer
    • Windowed watchdog timer
    • Wake timer
    • Microtick timer (UTICK)
    • OS event timer
    • RTC timer without external 32 kHz input
  • Communication Interfaces for Connectivity
    • 2x LPSPI, 4x LPI2C, 5x LPUART
    • 1x I3C
    • USB Full-speed (Device/Host) with on-chip FS PHY
    • 1x FlexCAN with FD
    • FlexIO

Security

  • EdgeLock Accelerator
    • PKC (Public Key Cryptography), supports ECC and RSA encryption and decryption
    • SGI (Secure Generic Interface), provides AES256, SHA-2 and key generation/derivation
    • Secure key store with key usage policies (protection of platform integrity, manufacturing and applications keys)
  • 128-bit Universal unique identifier (UUID) per device in accordance with IETF's RFC4122 version5 specification
  • Device life cycle management
  • Flash read/write/execute permission protect by MBC and lockable
  • Implicit-protected Flash Region (IFR)
  • Security Monitoring
    • Code watchdog for code flow integrity checking
    • Glitch attack resistant keyed access (Glikey) to security sensitive registers
    • 6x Passive anti tamper detect
  • Secure Installer for secure manufacturing and IP theft protection in untrusted factory

MCUXpresso Developer Experience

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Documentation

Quick reference to our documentation types

10 documents

Compact List

Application Note (4)
Data Sheet (1)
Errata (1)
Fact Sheet (1)
Reference Manual (2)
User Guide (1)

Design Resources

Design Files

Quick reference to our design files types.

2 design files

Hardware

Quick reference to our board types.

3 hardware offerings

Software

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5 software files

Note: For better experience, software downloads are recommended on desktop.

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