Dual Bidirectional Bus Buffer

Product Details

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Block Diagram

PCA9601 Block Diagram

PCA9601 Block Diagram


System Features

  • Bidirectional data transfer of I2C-bus signals
  • 15 mA SX/SY sink capability yields 5 V Fm+ bus rise time with 470 pF loads
  • Isolates capacitance allowing > 400 pF on SX/SY side and 4000 pF on TX/TY side
  • 1 MHz operation on up to 20 meters of wire (see AN10658)
  • Supply voltage range of 2.5 V to 15 V with I²C-bus logic levels on SX/SY side independent of supply voltage
  • Splits I²C-bus signal into pairs of forward/reverse TX/RX, TY/RY signals for interface with opto-electrical isolators and similar devices that need unidirectional input and output signal paths
  • Low power supply current
  • ESD protection exceeds 3500 V HBM per JESD22-A114, and 1400 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
  • Packages offered: SO8 and TSSOP8 (MSOP8)


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Design Resources

Design Files

4 design files

  • Models

    PCA9601DP IBIS model

  • Symbols and Footprints

    PCA9601D-SO8-CAD Symbol and PCB Footprint – BXL File

  • Symbols and Footprints

    PCA9601DP-TSSOP8-CAD Symbol and PCB Footprint – BXL File

  • Calculators

    NXP I2C Maximum Clock Speed Calculator


3 hardware offerings

Engineering Services

1 engineering service

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