Dual Bidirectional Bus Buffer

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Block Diagram

PCA9601 Block Diagram

PCA9601 Block Diagram

Features

  • Bidirectional data transfer of I²C-bus signals
  • 15 mA SX/SY sink capability yields 5 V Fm+ bus rise time with 470 pF loads
  • Isolates capacitance allowing > 400 pF on SX/SY side and 4000 pF on TX/TY side
  • 1 MHz operation on up to 20 meters of wire (see AN10658)
  • Supply voltage range of 2.5 V to 15 V with I²C-bus logic levels on SX/SY side independent of supply voltage
  • Splits I²C-bus signal into pairs of forward/reverse TX/RX, TY/RY signals for interface with opto-electrical isolators and similar devices that need unidirectional input and output signal paths
  • Low power supply current
  • ESD protection exceeds 3500 V HBM per JESD22-A114, and 1400 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
  • Packages offered: SO8 and TSSOP8 (MSOP8)

Target Applications

  • Interface between I²C-buses operating at different logic levels (for example, 5 V and 3 V or 15 V)
  • Interface between I²C-bus and SMBus (350 μA) standard or Fm+ standard
  • Simple conversion of I²C-bus SDA or SCL signals to multi-drop differential bus hardware, for example, via compatible PCA82C250
  • Interfaces with opto-couplers to provide opto-isolation between I²C-bus nodes up to 1 MHz
  • Long distance point-to-point or multipoint architectures

Design Resources

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