16-Bit I²C-Bus and SMBus I/O Port with Interrupt

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Block Diagram

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PCA9555 Block Diagram

PCA9555 Block Diagram

Block diagram: PCA9555BS, PCA9555D, PCA9555DB, PCA9555HF, PCA9555N, PCA9555PW

Features

System Features

  • Operating power supply voltage range of 2.3 V to 5.5 V
  • 5 V tolerant I/Os
  • Polarity Inversion register
  • Active LOW interrupt output
  • Low standby current
  • Noise filter on SCL/SDA inputs
  • No glitch on power-up
  • Internal power-on reset
  • 16 I/O pins which default to 16 inputs
  • 0 Hz to 400 kHz clock frequency
  • ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
  • Five packages offered: SO24, SSOP24, TSSOP24, HVQFN24 and HWQFN24

Design Resources

Documentation

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Hardware

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