Single-chip 32-bit microcontrollers; 128 kB ISP/IAP flash with 16/32/64 kB RAM

LPC2106FBD48
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  • This page contains information on a product that is not recommended for new designs.

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Block Diagram

Block diagram: LPC2104FBD48, LPC2105FBD48, LPC2106FBD48, LPC2106FHN48

Features

New features implemented in LPC2104/2105/2106/01 devices
  • Fast GPIO port enables port pin toggling up to 3.5 times faster than the original device and also allows for a port pin to be read at any time regardless of its function.
  • UART 0/1 include fractional baud rate generator, autobauding capabilities, and handshake flow-control fully implemented in hardware.
  • Buffered SSP serial controller supporting SPI, 4-wire SSI, and Microwire formats.
  • SPI programmable data length and leader mode enhancement.
  • Diversified Code Read Protection (CRP) enables different security levels to be implemented.
  • General purpose timers can operate as external event counters.

Key common features

  • 16/32-bit Arm7TDMI-S processor.
  • 16/32/64 kB on-chip static RAM.
  • 128 kB on-chip flash program memory. 128-bit-wide interface/accelerator enables high speed 60 MHz operation.
  • In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software. Flash programming takes 1 ms per 512 B line. Single sector or full chip erase takes 400 ms.
  • Vectored Interrupt Controller with configurable priorities and vector addresses.
  • EmbeddedICE-RT interface enables breakpoints and watch points. Interrupt service routines can continue to execute whilst the foreground task is debugged with the on-chip RealMonitor software.
  • Embedded Trace Macrocell enables non-intrusive high speed real-time tracing of instruction execution.
  • Multiple serial interfaces including two UARTs (16C550), Fast I²C-bus (400 kbit/s), and SPI.
  • Two 32-bit timers (7 capture/compare channels), PWM unit (6 outputs), Real Time Clock and Watchdog.
  • Up to thirty-two 5 V tolerant general purpose I/O pins in a tiny LQFP48 (7 mm x 7 mm) package.
  • 60 MHz maximum CPU clock available from programmable on-chip Phase-Locked Loop with settling time of 100 us.
  • The on-chip crystal oscillator should have an operating range of 1 MHz to 25 MHz.
  • Two low power modes, Idle and Power-down.
  • Processor wake-up from Power-down mode via external interrupt.
  • Individual enable/disable of peripheral functions for power optimization.
  • Dual power supply:
    • CPU operating voltage range of 1.65 V to 1.95 V (1.8 V +- 8.3 pct).
    • I/O power supply range of 3.0 V to 3.6 V (3.3 V +- 10 pct) with 5 V tolerant I/O pads.

Documentation

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Design Resources

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Design Files

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