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KV1x: Kinetis^® KV1x-75 MHz, Entry-level 3ph FOC / Sensorless Motor Control MCUs based on Arm^® Cortex^®-M0+

Overview

The Kinetis^® KV1x MCU family is the entry point of the V series. Built upon the Arm^® Cortex^®-M0+ core running at 75 MHz with hardware square root and divide capability, it delivers a 27% increase in performance in math-intensive applications versus comparable MCUs, allowing it to target BLDC as well as more computationally demanding PMSM motors. Additional features include integrated FlexCAN, dual 16-bit analog-to-digital controllers (ADCs) sampling at up to 1.2 mega samples per second (MS/s) in 12-bit mode, multiple motor control timers, up to 128 KB of flash memory and a comprehensive enablement suite from NXP^® and third-party resources, including reference designs, software libraries and motor configuration tools.

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Features

75 MHz Cortex-M0+ core with hardware square root and divide block— improves performance in math-intensive applications (e.g., processing of sensorless field-oriented control (FOC) algorithms)
4-channel DMA — reduced CPU loading for improved application performance
2x 16-bit ADCs with two capture and hold circuits and up to 1.2 MS/s samples rate in 12-bit mode — simultaneous measurement of current and voltage phase, reduced jitter on input values improving system accuracy 12-bit mode
Up to 2 x 6-channel and 4 x 2 -channel programmable FlexTimers — High-accuracy PWM generation with integrated power factor correction or speed sensor decoder (incremental decoder/hall sensor)
12-bit DAC and 2 x ACPMs (analog comparators)— over-current and over-voltage fault detection, reduced BOM costs. ADC and ACMP interconnect with PWM and PDB (programmable delay) blocks for real-time hardware control
Dual watchdogs — compliance with IEC 60730 safety regulation requirements
Broad family scalability with hardware and software compatibility — easy migration to more performance, memory and feature integration within the Kinetis^® V series

MoreLess

Features

75 MHz Cortex-M0+ core with hardware square root and divide block— improves performance in math-intensive applications (e.g., processing of sensorless field-oriented control (FOC) algorithms)
4-channel DMA — reduced CPU loading for improved application performance
2x 16-bit ADCs with two capture and hold circuits and up to 1.2 MS/s samples rate in 12-bit mode — simultaneous measurement of current and voltage phase, reduced jitter on input values improving system accuracy 12-bit mode
Up to 2 x 6-channel and 4 x 2 -channel programmable FlexTimers — High-accuracy PWM generation with integrated power factor correction or speed sensor decoder (incremental decoder/hall sensor)
12-bit DAC and 2 x ACPMs (analog comparators)— over-current and over-voltage fault detection, reduced BOM costs. ADC and ACMP interconnect with PWM and PDB (programmable delay) blocks for real-time hardware control
Dual watchdogs — compliance with IEC 60730 safety regulation requirements
Broad family scalability with hardware and software compatibility — easy migration to more performance, memory and feature integration within the Kinetis^® V series