LPC551x/S1x | Arm®Cortex®-M3 | NXP Semiconductors

Overview

The LPC551x/S1x MCU family is part of the EdgeVerse™ edge computing platform and expands the world’s first general purpose Cortex-M33-based MCU series, offering significant advantages for developers, including pin-, software- and peripheral-compatibility for ease of use and to accelerate time to market, while leveraging the cost-effective 40-nm NVM process technology.

The LPC551x/S1x is the baseline family within the LPC5500 MCU series inclusive of LPC5516x, LPC55S16x, LPC5514x, LPC55S14x, LPC5512x MCUs, providing new levels of cost and performance efficiency in addition to advanced security and system integration for industrial and general embedded markets.

Built with advanced security in mind, the LPC55S16 MCU is part of the Certified EdgeLock Assurance program and has been awarded Level 2 certifications by both the PSA Certified™ scheme co-developed by Arm and the GlobalPlatform Security Evaluation Standard for IoT Platforms (SESIP).

Features

Cortex-M33 Core

Running at a frequency of up to 150 MHz
TrustZone ^®, floating point unit (FPU) and memory protection unit (MPU)
Cortex-M33 built-in nested vectored interrupt controller (NVIC)
Nonmaskable interrupt (NMI) input with a selection of sources
Serial wire debug with eight breakpoints and four watch points. Includes serial wire output for enhanced debug capabilities
System tick timer

On-Chip Memory

Up to 256 KB on-chip flash program memory with flash accelerator and 256 byte page erase and write
Up to 96 KB total SRAM consisting of 16 KB SRAM on Code Bus, 64 KB SRAM on system bus (64 KB is contiguous), and additional 16 KB USB SRAM on system bus which can be used by the USB interface or for general-purpose use

Security Features

Arm TrustZone ^® enabled
PRINCE module for real-time encryption of data being written to on-chip flash and decryption of encrypted flash data during read to allow asset protection
CASPER crypto co-processor is provided to enable hardware acceleration for various functions required for certain asymmetric cryptographic algorithms, such as elliptic curve cryptography (ECC)
AES-256 encryption/decryption engine
Secure hash algorithm (SHA2) module supporting secure boot with dedicated DMA controller
Physical unclonable function (PUF) using dedicated SRAM for silicon fingerprint. PUF can generate, store, and reconstruct key sizes from 64 to 4096 bits. Includes hardware for key extraction
128-bit unique device serial number for identification (UUID)
Secure GPIO
True random number generator (TRNG)
Code watchdog

Serial Interfaces

FlexComm interface contains up to nine serial peripherals. Each FlexComm interface can be selected by software to be a USART, SPI, I²C, and I2S interface
I²C-bus interfaces support fast-mode and fast-mode plus with data rates of up to 1 Mbit/s and with multiple address recognition and monitor mode
USB 2.0 full speed host/device controller with on-chip PHY and dedicated DMA controller supporting crystal-less operation in device mode
USB 2.0 high-speed host/device controller with on-chip high-speed PHY

Digital Peripherals

DMA0 controller with 23 channels and up to 22 programmable triggers, able to access all memories and DMA-capable peripherals
DMA1 controller with 10 channels and up to 15 programmable triggers, able to access all memories and DMA-capable peripherals
CAN FD module with dedicated DMA controller
CRC engine block can calculate a CRC on supplied data using one of three standard polynomials with DMA support
Up to 64 general-purpose input/output (GPIO) pins
GPIO registers are located on the AHB for fast access. The DMA supports GPIO ports
Up to eight GPIOs can be selected as pin interrupts (PINT), triggered by rising, falling or both input edges
Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical (AND/OR) combination of input states
I/O pin configuration with support for up to 16 function options
Programmable logic unit (PLU) to create small combinational and/or sequential logic networks including state machines

Analog Peripherals

16-bit ADC with five differential channel pair (or 10 singled-ended channels), and with multiple internal and external trigger inputs and sample rates of up to 2.0 M samples/sec. The ADC supports two independent conversion sequences
Integrated temperature sensor connected to the ADC
Comparator with five input pins and external or internal reference voltage

Timers

Five 32-bit standard general-purpose asynchronous timers/counters, which support up to four capture inputs and four compare outputs. Specific timer events can be selected to generate DMA requests
One SCTimer/PWM with 8 input and 10 output functions (including 16 capture and match registers). Inputs and outputs can be routed to or from external pins and internally to or from selected peripherals. Internally, the SCTimer/PWM supports 16 match/captures, 16 events, and 32 states
32-bit real-time clock (RTC) with 1 s resolution running in the always-on power domain. Another timer in the RTC can be used for wake up from all low power modes including deep power-down, with 1 ms resolution
Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at up to four programmable, fixed rates
Windowed watchdog timer (WWDT) with FRO 1 MHZ as a clock source
Micro-tick timer running from the watchdog oscillator can be sued to wake up the device from sleep and deep-sleep modes
42-bit free running OS timer as continuous time-base for the system, available in any reduced power modes

Clock Generation

Internal free running oscillator (FRO)
32 kHz internal free running oscillator FRO
Internal low power oscillator (FRO 1 MHz)
Crystal oscillator with an operating frequency of 1 MHz to 25 MHz. Option for external clock input (bypass mode) for clock frequencies of up to 25 MHz
Crystal oscillator with 32.768 kHz operating frequency
PLL0 and LLL1 allows CPU operation up to the maximum CPU rate without the need for a high-frequency external clock
Clock output function with divider to monitor internal clocks
Frequency measurement unit for measuring the frequency of any on-chip or off-chip clock signal

Power-Saving Modes

Integrated power management unit (PMU) to minimize power consumption
Reduced power modes: Sleep, deep-sleep with RAM retention, power-down with RAM retention and CPU0 retention, and deep power-down with RAM retention
Configurable wake up options from peripheral interrupts
The micro-tick timer running from the watchdog oscillator, and the real-time clock (RTC) running from the 32.678 kHz clock, can be used to wake up the device from sleep and deep-sleep modes
Power-on reset (POR)
Brown-out-detectors (BOD) with separate thresholds for interrupt and forced reset

Additional Information

Operating from an internal DC-DC converter
Single power supply 1.8 V to 3.6 V
JTAG boundary scan supported
Operating temperature range -40 °C to +105 °C
Available in HLQFP100, VFBGA98 and HTQFP64 packages

Features

Cortex-M33 Core

Running at a frequency of up to 150 MHz
TrustZone ^®, floating point unit (FPU) and memory protection unit (MPU)
Cortex-M33 built-in nested vectored interrupt controller (NVIC)
Nonmaskable interrupt (NMI) input with a selection of sources
Serial wire debug with eight breakpoints and four watch points. Includes serial wire output for enhanced debug capabilities
System tick timer

On-Chip Memory

Up to 256 KB on-chip flash program memory with flash accelerator and 256 byte page erase and write
Up to 96 KB total SRAM consisting of 16 KB SRAM on Code Bus, 64 KB SRAM on system bus (64 KB is contiguous), and additional 16 KB USB SRAM on system bus which can be used by the USB interface or for general-purpose use

Security Features

Arm TrustZone ^® enabled
PRINCE module for real-time encryption of data being written to on-chip flash and decryption of encrypted flash data during read to allow asset protection
CASPER crypto co-processor is provided to enable hardware acceleration for various functions required for certain asymmetric cryptographic algorithms, such as elliptic curve cryptography (ECC)
AES-256 encryption/decryption engine
Secure hash algorithm (SHA2) module supporting secure boot with dedicated DMA controller
Physical unclonable function (PUF) using dedicated SRAM for silicon fingerprint. PUF can generate, store, and reconstruct key sizes from 64 to 4096 bits. Includes hardware for key extraction
128-bit unique device serial number for identification (UUID)
Secure GPIO
True random number generator (TRNG)
Code watchdog

Serial Interfaces

FlexComm interface contains up to nine serial peripherals. Each FlexComm interface can be selected by software to be a USART, SPI, I²C, and I2S interface
I²C-bus interfaces support fast-mode and fast-mode plus with data rates of up to 1 Mbit/s and with multiple address recognition and monitor mode
USB 2.0 full speed host/device controller with on-chip PHY and dedicated DMA controller supporting crystal-less operation in device mode
USB 2.0 high-speed host/device controller with on-chip high-speed PHY

Digital Peripherals

DMA0 controller with 23 channels and up to 22 programmable triggers, able to access all memories and DMA-capable peripherals
DMA1 controller with 10 channels and up to 15 programmable triggers, able to access all memories and DMA-capable peripherals
CAN FD module with dedicated DMA controller
CRC engine block can calculate a CRC on supplied data using one of three standard polynomials with DMA support
Up to 64 general-purpose input/output (GPIO) pins
GPIO registers are located on the AHB for fast access. The DMA supports GPIO ports
Up to eight GPIOs can be selected as pin interrupts (PINT), triggered by rising, falling or both input edges
Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical (AND/OR) combination of input states
I/O pin configuration with support for up to 16 function options
Programmable logic unit (PLU) to create small combinational and/or sequential logic networks including state machines

Analog Peripherals

16-bit ADC with five differential channel pair (or 10 singled-ended channels), and with multiple internal and external trigger inputs and sample rates of up to 2.0 M samples/sec. The ADC supports two independent conversion sequences
Integrated temperature sensor connected to the ADC
Comparator with five input pins and external or internal reference voltage

Timers

Five 32-bit standard general-purpose asynchronous timers/counters, which support up to four capture inputs and four compare outputs. Specific timer events can be selected to generate DMA requests
One SCTimer/PWM with 8 input and 10 output functions (including 16 capture and match registers). Inputs and outputs can be routed to or from external pins and internally to or from selected peripherals. Internally, the SCTimer/PWM supports 16 match/captures, 16 events, and 32 states
32-bit real-time clock (RTC) with 1 s resolution running in the always-on power domain. Another timer in the RTC can be used for wake up from all low power modes including deep power-down, with 1 ms resolution
Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at up to four programmable, fixed rates
Windowed watchdog timer (WWDT) with FRO 1 MHZ as a clock source
Micro-tick timer running from the watchdog oscillator can be sued to wake up the device from sleep and deep-sleep modes
42-bit free running OS timer as continuous time-base for the system, available in any reduced power modes

Clock Generation

Internal free running oscillator (FRO)
32 kHz internal free running oscillator FRO
Internal low power oscillator (FRO 1 MHz)
Crystal oscillator with an operating frequency of 1 MHz to 25 MHz. Option for external clock input (bypass mode) for clock frequencies of up to 25 MHz
Crystal oscillator with 32.768 kHz operating frequency
PLL0 and LLL1 allows CPU operation up to the maximum CPU rate without the need for a high-frequency external clock
Clock output function with divider to monitor internal clocks
Frequency measurement unit for measuring the frequency of any on-chip or off-chip clock signal

Power-Saving Modes

Integrated power management unit (PMU) to minimize power consumption
Reduced power modes: Sleep, deep-sleep with RAM retention, power-down with RAM retention and CPU0 retention, and deep power-down with RAM retention
Configurable wake up options from peripheral interrupts
The micro-tick timer running from the watchdog oscillator, and the real-time clock (RTC) running from the 32.678 kHz clock, can be used to wake up the device from sleep and deep-sleep modes
Power-on reset (POR)
Brown-out-detectors (BOD) with separate thresholds for interrupt and forced reset

Additional Information

Operating from an internal DC-DC converter
Single power supply 1.8 V to 3.6 V
JTAG boundary scan supported
Operating temperature range -40 °C to +105 °C
Available in HLQFP100, VFBGA98 and HTQFP64 packages

LPC55S16-EVK:LPCXpresso55S16 Development Board

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LPC551x/S1x: Baseline Arm^® Cortex^®-M33-Based Microcontroller Family

Overview

Features

Cortex-M33 Core

On-Chip Memory

Security Features

Serial Interfaces

Digital Peripherals

Analog Peripherals

Timers

Clock Generation

Power-Saving Modes

Additional Information

Features

Cortex-M33 Core

On-Chip Memory

Security Features

Serial Interfaces

Digital Peripherals

Analog Peripherals

Timers

Clock Generation

Power-Saving Modes

Additional Information

LPC551x/S1x MCU Family Block Diagram.

MCU Minutes | CANopen and CANopen FD in the MCUXpresso SDK

LPC55S16 MCU | Security Certification

LPC551x/S1x MCU Family Block Diagram.

MCU Minutes | CANopen and CANopen FD in the MCUXpresso SDK

LPC55S16 MCU | Security Certification

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LPC551x/S1x: Baseline Arm® Cortex®-M33-Based Microcontroller Family

Overview

Features

LPC551x/S1x MCU Family Block Diagram.

MCU Minutes | CANopen and CANopen FD in the MCUXpresso SDK

LPC55S16 MCU | Security Certification

LPC551x/S1x MCU Family Block Diagram.

MCU Minutes | CANopen and CANopen FD in the MCUXpresso SDK

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LPC551x/S1x: Baseline Arm^® Cortex^®-M33-Based Microcontroller Family