QorIQ® P1022

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P1022 device is "Not recommended for new designs", please use the replacement families Power Architecture (T1013, T1023), Arm Architecture (LS1012A, LS1023A).

The QorIQ^® P1022 family of processors is designed to deliver complex application processing performance with exceptional feature integration and high-speed connectivity for IP networking and advanced media processing applications. This device combines dual e500 processor cores built on Power Architecture^® technology with enhanced system peripherals and interconnects technology to balance processor performance with I/O system throughput. The P1013 is a single-core version of the P1022 family.

Ideally suited for the printing and imaging market, the P1022 processor includes advanced deep sleep power and energy management features that enable developers to design next-generation energy efficiency, environmental and governmental energy regulatory power requirements. This innovative deep sleep function enables <1W system designs where the P1022 processor is able to continue to receive packets and perform fast recovery from an extremely low-power sleep mode.

Data Sheet

Reference Manual

Product Details

Block Diagram

NXP QorIQ P1022/13 Communication Processor Block Diagram

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Features

Core Complex

Dual (P1022) or single (P1013) high-performance Power Architecture e500 cores
Core frequencies from 667 MHz to 1200 MHz
32 KB L1 I/D caches
256 KB L2 cache with ECC.
- Also configurable as SRAM and stashing memory

Networking Elements

Two 10/100/1000 Mbps enhanced three-speed Ethernet controllers (eTSECs)
High-speed interfaces supporting various multiplexing options:
- Six SerDes up to 3.125 GHz multiplexed across controllers
- Three PCI Express^{^®} interfaces
- Two SGMII interfaces
- Two serial ATA interfaces

Accelerators and Memory Control

32/64-bit DDR2/DDR3 SDRAM memory controller with ECC support
Integrated security engine
- Protocol support includes SNOW, ARC4, 3DES, AES, RSA/ECC, RNG, single-pass SSL/TLS, Kasumi, XOR acceleration

Basic Peripherals and Interconnect

Dual high-speed USB controllers (USB 2.0)
eLBC, TDM, I²S, eSDHC, Dual I²C, DUART, PIC, DMA, GPIO

Additional Features

LCD interface supporting a display of 1280 x 1024P
- @ 60 Hz, 24 bits per pixel
Advanced power management

Comparison Table

	P1013	P1022
Cores	1	2
Core Frequency	667 - 1067 MHz	667 - 1067 MHz
L2 Cache	256KB	256KB
DDR	32/64-bit DDR2/DDR3	32/64-bit DDR2/DDR3
GbE	2 x 10/100/1000	2 x 10/100/1000
PCIe Gen 1.0	2 controllers w/ 4 SERDES	2 controllers w/ 4 SERDES
USB 2.0	2	2
Memory Card	SD/MMC	SD/MMC
Other interfaces	Dual- SATA, LCD I/F, SPI, 2xI²C, DUART	Dual- SATA, LCD I/F, SPI, 2xI²C, DUART
Accelerators	SEC3.1	SEC3.1

Documentation

Quick reference to our documentation types.

1-5 of 42 documents

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^{Fact Sheet}
P1013/P1022 Fact SheetFeatured

PDFRev 1Jan 13, 2011273.1 KBQP1022FSEnglish
^{Data Sheet}
P1013 QorIQ Integrated Processor Hardware Specifications - Data sheet

PDFRev 2Sep 25, 20131.2 MBP1013ECEnglish
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^{Data Sheet}
P1022 QorIQ Integrated Processor Hardware Specifications - Data sheet

PDFRev 2Sep 25, 20131.2 MBP1022ECEnglish
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^{Reference Manual}
EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual

PDFRev 1Jun 26, 201410.4 MBEREF_RMEnglish
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^{Reference Manual}
P1022 QorIQ Integrated Processor Reference Manual

PDFRev 2Apr 1, 201326.5 MBP1022RMEnglish
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^{Reference Manual}
PowerPC ™ e500 Core Family - Reference Manual

PDFRev 1May 11, 20055.7 MBE500CORERMEnglish
^{Application Note}
AN5079, QorIQ P1 Series to T1 Series Migration Guide - Application Note

PDFRev 0Jul 24, 2017349.9 KBAN5079English
^{Application Note}
AN5125, Introduction to Device Trees - Application Note

PDFRev 0Sep 3, 2015566.4 KBAN5125English
^{Application Note}
AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note

PDFRev 4Nov 11, 2014468.7 KBAN4039English
^{Application Note}
AN4343, P1022 QorIQ Integrated Processor Design Checklist - Application Note

PDFRev 1Jun 2, 2014464.6 KBAN4343English
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^{Application Note}
AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes

PDFRev 0Jan 21, 20141.2 MBAN4848English
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^{Application Note}
AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes

PDFRev 2Dec 16, 2013269.4 KBAN4531English
^{Application Note}
AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note

PDFRev 6Nov 25, 2013547.7 KBAN3940English
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^{Application Note}
QorIQ eSPI Controller Register Setting Considerations and Programming Examples

PDFRev 1Jun 21, 2012216.6 KBAN4375English
^{Application Note}
Booting from On-Chip ROM (eSDHC or eSPI)

PDFRev 2Jun 15, 2012334.2 KBAN3659English
^{Application Note}
Verification of the IEEE 1588 Interface

PDFRev 0Jul 6, 2011743.2 KBAN4326English
^{Application Note}
SerDes Reference Clock Interfacing and HSSI Measurements Recommendations

PDFRev Rev. 0May 13, 2011577.2 KBAN4311English
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^{Application Note}
Support for IEEE 1588™ Protocol in PowerQUICC and QorIQ Processors

PDFRev 0Oct 6, 2010142.0 KBAN3423English
^{Application Note}
DDR Interleaving for PowerQUICC and QorIQ Processors

PDFRev 1Jun 30, 2010717.3 KBAN3939English
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^{Application Note}
Downloading Microcode On QUICC Engine™ Block-Enabled Devices

PDFRev 1Apr 1, 2010187.2 KBAN3946English
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^{Application Note}
AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes

PDFRev 0Mar 28, 2010576.8 KBAN4064English
^{Application Note}
Understanding SYSCLK Jitter

PDFRev 1Feb 18, 2010514.4 KBAN4056English
^{Application Note}
The SystemID Format for Power Architecture™ Development Systems

PDFRev 2Oct 26, 2009495.3 KBAN3638English
^{Application Note}
Booting from Serial RapidIO™/PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx

PDFRev 0Oct 21, 2009543.1 KBAN3646English
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^{Application Note}
MPC603e and e500 Register Model Comparison

PDFRev 1Sep 23, 2009612.9 KBAN2490English
^{Application Note}
Implementing SGMII Interfaces on the PowerQUICC™ III

PDFRev 0Jun 5, 2009692.4 KBAN3869English
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^{Application Note}
AN3542, SMP Boot Process for Dual E500 Cores - Application Notes

PDFRev 0Jan 25, 2008519.9 KBAN3542English
^{Application Note}
PowerQUICC™ Data Cache Coherency

PDFRev 0Dec 21, 2007547.7 KBAN3544English
^{Application Note}
Coherency and Synchronization Requirements for PowerQUICC™ III

PDFRev 1Dec 17, 2007189.0 KBAN3441English
^{Application Note}
Error Correction and Error Handling on PowerQUICC (TM) III Processors

PDFRev 0Nov 27, 2007573.0 KBAN3532English
^{Application Note}
AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes

PDFRev 0Oct 31, 2007935.0 KBAN3445English
^{Application Note}
AN3531, Migrating from e600- to e500-Based Integrated Devices - Application Notes

PDFRev 0Oct 31, 2007961.6 KBAN3531English
^{Application Note}
Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces

PDFRev 2Mar 27, 2007619.7 KBAN2910English
^{Application Note}
AN2665, e500 Software Optimization Guide (eSOG) - Application Notes

PDFRev 0Apr 8, 2005799.6 KBAN2665English
^{Application Note Software}
Challenges in Testing for Power Rail Shorts with New Technologies

PDFRev 0Jun 13, 2007163.7 KBAN3372English
^Brochure
Digital Signage: A Sign of the Times

PDFRev 0Jan 16, 20121.2 MBPWRARBYNDBITSDSEnglish
^{Fact Sheet}
Overview of the P1022RDK

PDFRev 3Sep 21, 2011443.5 KBQP1022RDKFSEnglish
^{Supporting Information}
FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP^® Cryptographic Accelerators - White Paper

PDFRev 1.9Oct 28, 2016303.5 KBFSLNISTCAVPEnglish
^{Supporting Information}
P1020 and P1021 Family Customer Export Control Information

PDFRev 2Dec 10, 2010246.8 KBP102XFAMPECIEnglish
^{Supporting Information}
P1022 Family Customer Export Control Information

PDFRev 2Dec 10, 2010246.7 KBP1022FAMPECIEnglish
^{White Paper}
QORIQPMWP, QorIQ Power Management - White Paper

PDFRev 0Mar 30, 20171.4 MBQORIQPMWPEnglish
^{White Paper}
Low-Power Network Standby in the Home and Office - White Paper

PDFRev 0May 8, 2013160.2 KBLPOENETSTBYHOWPEnglish

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Design Resources

Design Files

1 design file

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^Models
P1022 IBIS Model

ZIPRev 1Feb 25, 2010128 KBP1022IBIS
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