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Join our teamQorIQ® P1025/16 Single- and Dual-Core Multi-Protocol Communications Processors
Overview
Features
Features
Core Complex
- Dual (P1025) or single (P1016) high-performance Power Architecture® e500 cores, 32 KB L1 cache, up to 667 MHz
- 256 KB L2 cache with ECC, also configurable as SRAM and stashing memory
Networking Elements
- Three 10/100/1000 enhanced three speed Ethernet controllers (eTSEC)
- Two SGMII interfaces
- Support for IEEE® 1588
- QUICC Engine® module supporting:
- UTOPIA-L2
- Four T1/E1/HDLC
- Two 10/100 Ethernet
Accelerators and Memory Control
- DDR3 32-bit memory controller with ECC support
- Integrated security engine
- Protocol support includes SNOW, ARC4, 3DES, AES, RSA/ECC, RNG, single-pass SSL/TLS, Kasumi
- XOR acceleration
Basic Peripherals and Interconnect
- Four-lane SERDES up to 3.125 GHz multiplexed across controllers
- Two PCI Express® Gen1.0 interface controllers
- Two USB2.0 controllers
- Enhanced Local Bus Controller (eLBC)
- TDM
- eSDHC
- Dual I²C, DUART, PIC, DMA, GPIO
Additional Features
- Support for PROFIBUS
- NXP® Product Longevity Program
- 561-pin 31x31 mm TePBGA package
Development Boards
Development Boards
TWR-P1025:QorIQ® P1 MPU Tower® System Module.
Target Applications
Communication Infrastructure
Industrial
Mobile
Smart City
Smart Home
- Personal/Consumer NAS
- Smart Home Gateway
Comparison Table
| P1015 | P1016 | P1024 | P1025 | |
|---|---|---|---|---|
| Cores | 1 | 1 | 2 | 2 |
| Core Frequency | 400 - 667 MHz | 400 - 667 MHz | 400 - 533 MHz | 400 - 533 MHz |
| L2 Cache | 256KB | 256KB | 256KB | 256KB |
| DDR | 32-bit DDR2/DDR3 | 32-bit DDR2/DDR3 | 32-bit DDR2/DDR3 | 32-bit DDR2/DDR3 |
| GbE | 3 x 10/100/1000 | 3 x 10/100/1000 | 3 x 10/100/1000 | 3 x 10/100/1000 |
| PCIe Gen 1.0 | 2 | 2 | 2 | 2 |
| USB 2.0 | 2 | 1 | 2 | 1 |
| Memory Card | SD/MMC | SD/MMC | SD/MMC | SD/MMC |
| Other interfaces | SPI, 2xI2C, DUART | SPI, 2xI2C, DUART | SPI, 2xI2C, DUART | SPI, 2xI2C, DUART |
| TDM or QUICC Engine | TDM | QUICC Engine | TDM | QUICC Engine |
| Accelerators | SEC3.3 | SEC3.3 | SEC3.3 | SEC3.3 |