QorIQ® P2020

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P2010 and P2020 devices are "Not recommended for new designs", please use the replacement families Power Architecture (T1013, T1023), Arm Architecture (LS1012A, LS1023A).

The QorIQ^® P2020 and P2010 communications processors deliver high performance per watt for dual- and single-core applications. Using advanced 45nm process technology these CPUs reach frequencies up to 1.33GHz.

Pin-compatible with the QorIQ P1 family devices, the P2020 and P2010 devices offer four interchangeable cost-effective solutions, scaling from a single core at 533 MHz (P1011) to a dual core at 1.33 GHz (P2020) and delivering an impressive 4.5x aggregate frequency range within the same pinout.

Data Sheet

Reference Manual

Product Details

Block Diagram

Freescale QorIQ P2020/10 Communication Processor Block Diagram

Get diagram PDF

Features

Core Complex

Dual (P2020) or single (P2010) high-performance Power Architecture^{^®} e500 cores
Up to 1.33 GHz
32 KB L1 and 512KB L2 caches

Networking Elements

Three 10/100/1000 Mbps enhanced three-speed Ethernet controllers (eTSECs)
Four SerDes up to 3.125 GHz multiplexed across controllers supporting:
- Two PCI Express^{^®} interfaces
- Two Serial RapidIO^® interfaces
- Two SGMII interfaces

Accelerators and Memory Control

Integrated security engine
Protocol support includes SNOW, ARC4, 3DES, AES, RSA/ECC, RNG, single-pass SSL/TLS, Kasumi, XOR acceleration

Basic Peripherals and Interconnect

Dual high-speed USB controllers (USB 2.0)
eLBC, eSDHC, Dual I²C, DUART, PIC, DMA, GPIO

Additional Features

Package: 689-pin temperature-enhanced plastic BGA (TEPBGA2)
0C to 125C Tj -40C to 125C Tj option

Comparison Table

	P2010	P2020
Cores	1	2
Core Frequency	800 - 1200 MHz	800 - 1200 MHz
L2 Cache	512KB	512KB
DDR	32/64-bit DDR2/DDR3	32/64-bit DDR2/DDR3
GbE	3 x 10/100/1000	3 x 10/100/1000
PCIe Gen 1.0	3 controllers w/ 4 SERDES	3 controllers w/ 4 SERDES
sRIO 1.2	2 x1 or 1 x4	2 x1 or 1 x4
USB 2.0	1	1
Memory Card	SD/MMC	SD/MMC
Other interfaces	SPI, 2xI²C, DUART	SPI, 2xI²C, DUART
Accelerators	SEC3.1	SEC3.1

Design Resources

Design Files

1 design file

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^Models
P2020 BSDL Model

ZIPRev AJan 14, 201311.5 KBP2020BSDL
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Hardware

4 hardware offerings

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^{Evaluation and Development Boards}
P2020 Reference Design BoardFeatured

P2020RDB
^{Evaluation and Development Boards}
P2020 Development System Featured

P2020DS
^{Emulators, Probes, and Programmers}
Power Architecture^® processor ( COP ) Probe Tips for CodeWarrior^® TAP

CWH-CTP-COP-YE
^{Emulators, Probes, and Programmers}
CodeWarrior^® TAP

CW_TAP