QorIQ® P2020 and P2010 Dual- and Single-Core Communications Processors

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Block Diagram

Freescale QorIQ P2020/10 Communication Processor Block Diagram

Freescale QorIQ P2020/10 Communication Processor Block Diagram


Core Complex

  • Dual (P2020) or single (P2010) high-performance Power Architecture® e500 cores
  • Up to 1.33 GHz
  • 32 KB L1 and 512KB L2 caches

Networking Elements

  • Three 10/100/1000 Mbps enhanced three-speed Ethernet controllers (eTSECs)
  • Four SerDes up to 3.125 GHz multiplexed across controllers supporting:
    • Two PCI Express® interfaces
    • Two Serial RapidIO® interfaces
    • Two SGMII interfaces

Accelerators and Memory Control

  • Integrated security engine
  • Protocol support includes SNOW, ARC4, 3DES, AES, RSA/ECC, RNG, single-pass SSL/TLS, Kasumi, XOR acceleration

Basic Peripherals and Interconnect

  • Dual high-speed USB controllers (USB 2.0)

Additional Features

  • Package: 689-pin temperature-enhanced plastic BGA (TEPBGA2)
  • 0C to 125C Tj -40C to 125C Tj option

Part numbers include: P2010NSE2HFC, P2010NSE2HHC, P2010NSE2KHC, P2010NSE2MFC, P2010NSE2MHC, P2010NSE2NHC, P2010NSN2HFC, P2010NSN2HHC, P2010NSN2KFC, P2010NSN2KHC, P2010NSN2MFC, P2010NSN2MHC, P2010NSN2NHC, P2010NXE2HFC, P2010NXE2KFC, P2010NXE2KHC, P2010NXE2MHC, P2010NXN2HFC, P2010NXN2KFC, P2010NXN2KHC, P2010NXN2MHC, P2020NSE2HFC, P2020NSE2KFC, P2020NSE2KHC, P2020NSE2MFC, P2020NSE2MHC, P2020NSE2NHC, P2020NSN2HFC, P2020NSN2HHC, P2020NSN2KFC, P2020NSN2KHC, P2020NSN2MFC, P2020NSN2MHC, P2020NSN2NHC, P2020NXE2HFC, P2020NXE2HHC, P2020NXE2KFC, P2020NXE2KHC, P2020NXE2MHC, P2020NXN2HFC, P2020NXN2KFC, P2020NXN2KHC, P2020NXN2MHC.

Comparison Table

P2010 P2020
Cores 1 2
Core Frequency 800 - 1200 MHz 800 - 1200 MHz
L2 Cache 512KB 512KB
DDR 32/64-bit DDR2/DDR3 32/64-bit DDR2/DDR3
GbE 3 x 10/100/1000 3 x 10/100/1000
PCIe Gen 1.0 3 controllers w/ 4 SERDES 3 controllers w/ 4 SERDES
sRIO 1.2 2 x1 or 1 x4 2 x1 or 1 x4
USB 2.0 1 1
Memory Card SD/MMC SD/MMC
Other interfaces SPI, 2xI2C, DUART SPI, 2xI2C, DUART
Accelerators SEC3.1 SEC3.1


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