QorIQ^® P1023/17 Low-End Single- and Dual-Core Communications Processors with Data Path

Overview

The P1023 and P1017 processors offer the unique value of integrated high-performance data path offload for networking protocols and dual e500 Power Architecture^® cores for application software. The P1023 and P1017 are ideally suited for high-performance enterprise WLAN, fixed routers and security gateway applications. The P1023 device supports a 400–800 MHz performance range, along with advanced security and a rich set of interfaces—all delivered on 45 nm technology for low-power implementation.

The P1023 processor includes a performance-optimized implementation of the QorIQ^® data path acceleration architecture (DPAA). This architecture provides the infrastructure to support simplified sharing of networking interfaces and accelerators by multiple CPU cores. The DPAA significantly reduces software overhead associated with high touch packet forwarding operations. Examples of the types of packet processing services this architecture is optimized to support include traditional routing and bridging, firewall, VPN termination for IPsec and MACsec (a standardized form of Ethernet encapsulation that can be used to provide confidentiality).

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Features

CORE COMPLEX

Dual (P1023) or single (P1017) high-performance
Power Architecture e500v2 cores
Dual-core 500MHz or single-core up to 800MHz
32 KB instruction and data L1 caches
Double-precision floating-point support
256 KB L2 cache with ECC.
- Also configurable as SRAM and stashing memory

NETWORKING ELEMENTS

High-speed interfaces supporting various multiplexing options:
- Four SerDes up to 3.125 GHz multiplexed across controllers
- Two 10/100/1000 Mbps three-speed Ethernet controllers (TSECs)
- Three PCI Express^® interfaces
- Two SGMII interfaces

ACCELERATORS AND MEMORY CONTROL

32-bit DDR3/DDR3L SDRAM memory controller
DPAA incorporating acceleration for the following functions:
- Packet parsing, classification and distribution queue management for scheduling, packet sequencing and congestion management hardware buffer management for buffer allocation and de-allocation
Integrated security engine
- Protocol support includes single pass encryption & message authentication for common security protocols (IPsec, SSL, SRTP, DTLS), XOR acceleration

BASIC PERIPHERALS AND INTERCONNECT

High-speed USB controller (USB 2.0) host and device support
ULPI interface to PHY
eLBC, Dual I²C, DUART, PIC, DMA, GPIO x16

ADDITIONAL FEATURES

Support for a hardware MACSEC enabled interface
Support for IEEE^® 1588

PACKAGE

457-pin temperature-enhanced plastic BGA (TEPBGA1)
Standard and extended temp support: -40C to 105C Tj

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Features

CORE COMPLEX

Dual (P1023) or single (P1017) high-performance
Power Architecture e500v2 cores
Dual-core 500MHz or single-core up to 800MHz
32 KB instruction and data L1 caches
Double-precision floating-point support
256 KB L2 cache with ECC.
- Also configurable as SRAM and stashing memory

NETWORKING ELEMENTS

High-speed interfaces supporting various multiplexing options:
- Four SerDes up to 3.125 GHz multiplexed across controllers
- Two 10/100/1000 Mbps three-speed Ethernet controllers (TSECs)
- Three PCI Express^® interfaces
- Two SGMII interfaces

ACCELERATORS AND MEMORY CONTROL

32-bit DDR3/DDR3L SDRAM memory controller
DPAA incorporating acceleration for the following functions:
- Packet parsing, classification and distribution queue management for scheduling, packet sequencing and congestion management hardware buffer management for buffer allocation and de-allocation
Integrated security engine
- Protocol support includes single pass encryption & message authentication for common security protocols (IPsec, SSL, SRTP, DTLS), XOR acceleration