QorIQ® P4080/P4040/P4081 Multicore Communications Processors

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Product Details

Block Diagram

P4080 40 81 BD IMG

QoriQ P4080/P4040/P4081 Block Diagram

Features

Core Complex

  • Four to eight high-performance e500mc cores up to 1.5 GHz
  • Three-level cache-hierarchy: 32 KB I/D L1, 128 KB private L2 per core, 2 MB shared L3
  • Hardware hypervisor for safe partitioning of operating systems between cores

Networking Elements

  • High-speed peripheral interfaces
    • Three PCI Express® v2.0 controllers/ports running at up to 5 GHz
    • Two Serial RapidIO® 1.2 controllers/ports running at up to 3.125 GHz

Accelerators and Memory Control

  • Dual 64-bit (72-bit with ECC) DDR2/3 memory controllers up to 1.3 GHz data rate
  • DPAA incorporating acceleration for the following functions
    • Packet parsing, classification, and distribution
    • Queue management for scheduling, packet sequencing, and congestion management
    • Hardware buffer management for buffer allocation and de-allocation
    • Encryption (SEC 4.0)
    • RegEx Pattern Matching (PME 2.0)
  • Ethernet interfaces
    • Two 10 Gbps Ethernet (XAUI) controllers
    • Eight 1 Gbps Ethernet (SGMII) controllers

Basic Peripherals and Interconnect

  • SD/MMC,
  • Two dual UARTs (DUART),
  • Four I²C,
  • Two USB 2.0 with integrated PHY
  • Enhanced local bus controller (eLBC)
  • Serial peripheral interface (SPI) controller, four I²C controllers, two dual UARTs (DUART),
  • Multicore programmable interrupt controller (PIC)
  • Two 4-channel DMA engines

Additional Features

  • Trusted boot capability to ensure only the correct code is booted and that code is not reverse-engineered
  • Pin-and software-compatible with P3041, P4040, P5010 and P5020
  • This product is included in NXP's product longevity program, with assured supply for a minimum of 10 years after launch

Comparison Table

P4040 P4081 P4080
Cores 4 8 4
Core Frequency 1200 - 1500 MHz 1000 - 1200 MHz 1200 - 1500 MHz
L2 Cache 128KB/Core 128KB/Core 128KB/Core
L3 Cache 2x 1MB Frontside 8 way cache allocation 2x 1MB Frontside 8 way cache allocation 2x 1MB Frontside 8 way cache allocation
DDR 2 x 64-bit DDR2/DDR3 2 x 64-bit DDR2/DDR3 2 x 64-bit DDR2/DDR3
GbE 8 x 1 GbE + 2 x 10 10 GbE 8 x 1 GbE + 2 x 10 10 GbE 8 x 1 GbE + 2 x 10 10 GbE
PCIe Gen 1.0 3 PCIe Controllers (x8, x4) 3 PCIe Controllers (x8, x4) 3 PCIe Controllers (x8, x4)
USB 2.0 2 2 2
sRIO 1.2 Serial x4/x1 Serial x4/x1 Serial x4/x1
Security SEC 4.0 SEC 4.0
Accelerators PME 2.0 DPAA (FMan, QMan, BMan) PME 2.0 DPAA (FMan, QMan, BMan) PME 2.0 DPAA (FMan, QMan, BMan)

Design Resources

Documentation

Quick reference to our documentation types.

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Hardware

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Software

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Note: For better experience, software downloads are recommended on desktop.

Engineering Services

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To find a complete list of our partners that support this product, please see our Partner Marketplace.

Training

2 trainings

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