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Join our teamLayerscape® 1020A and 1022A Dual-Core Processors
Overview
Features
Features
Core Complex
- Dual Arm® v7 Cortex®-A7 32-bit cores, each supporting dual precision floating point and NEONSIMD module running up to 1.2 GHz (LS1020A) or 600 MHz (LS1022A)
- 32 KB instruction and data L1 cache with single bit error detection and correction, ECC protection on both instruction and data caches
- Up to 512 KB coherent L2 cache with single bit error detection and correction, ECC protection
Networking Elements
- SerDes
- 4 lane at up to 6 GHz (LS1020A)
- Supports SGMII, PCIe and SATA
- Ethernet
- 1 lane at up to 5 GHz (LS1022A)
- Supports PCIe®
- 4 lane at up to 6 GHz (LS1020A)
- Three virtualized enhanced triple-speed Ethernet controllers (VeTSEC) supporting SGMII (up to 2),RGMII, RMII, MII (LS1020A)
- Support IEEE® 1588
- Two virtualized enhanced triple-speed Ethernet controllers (VeTSEC) supporting RGMII, RMII, MII
- Support IEEE 1588
- Two PCIe Gen2 controllers (LS1020A)
- Supporting up to 5G/tps in 1-lane, 2-lane, or 4-lane (with a single controller)
- MSI supported
- One PCIe Gen2 controller
- Supporting up to 5G/tps in 1-lane
- MSI supported
Accelerators and Memory Control
- DDR memory controller supports DDR3L and DDR4 at up to 1600 MHz (LS1020A)
- 8-bit, 16-bit, 32-bit memory supported, with ECC support
- DDR memory controller supports DDR3L at up to 1000 MHz
- 8-bit, 16-bit memory supported, with ECC support
- Security Engine (SEC5.4) features five cryptographic hardware acceleration modules, true random number generator, hashing and CRC unit.
Basic Peripherals and Interconnect
- Arm Cache Coherent Interconnect (CCI400)
- Arm AMBA4 MPCore Virtualization
- Integrated Flash controller supporting 16-bit interface
- QuadSPI Flash controller
- USB3.0 superspeed controller with integrated PHY, supporting OTG, Host and Device modes (LS1020A)
- USB2.0 controller supporting OTG, Host and Device modes
- SD/MMC controller
- SATA3 controller supporting 6G/tps
- 3x I²C
- 2x SPI
NXP Layerscape 1022A Processor block diagram
NXP Priority Support- helping you to get to market faster
NXP Layerscape 1020A Processor block diagram
LS1 Family and IoT Synergy at ArmTeck - Interview
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NXP Layerscape 1022A Processor block diagram -
NXP Priority Support- helping you to get to market faster -
NXP Layerscape 1020A Processor block diagram
-
LS1 Family and IoT Synergy at ArmTeck - Interview
29841_LS1022A_BD
29841_LS1020A_BD
Development Boards and Designs
Development Boards and Designs
TWR-LS1021A:Layerscape LS1021A Tower® System Module.
Target Applications
Communication Infrastructure
- Broadband Modem and Residential Gateway
- Energy Gateway
- Enterprise Access Point
Industrial
Smart Home
- Personal/Consumer NAS
Technologies
Comparison Table
| LS1021A | LS1020A | LS1022A | |
|---|---|---|---|
| Cores | 2 | 2 | 2 |
| Core Frequency | Up to 1.2 GHz | Up to 1.2 GHz | Up to 600 MHz |
| SerDes | 4 Lanes | 4 Lanes | 1 Lanes |
| Security | SEC 5.4 | SEC 5.4 | SEC 5.4 |
| DDR 4 | Yes | Yes | No |
| USB 3.0 | Yes | Yes | No |
| LCD Support | Yes | No | No |
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Similar Products
We recommend the following Power Management IC for LS1020A and LS1022A Processors
Select the specifications below to find the perfect fit for your design
| PMIC Part Number | Description | External Memory Voltage (V) | Ambient Operating Temperature (Min-Max) (°C) | Qualification Tier |
|---|---|---|---|---|
| MC34VR500V1ES | Regulator, Buck, Quad with up to 4.5A Output and Triple User-programmable LDOs, QFN 56 | 1.35 | -40 to 105 | Industrial |
| MC34VR500V2ES | Regulator, Buck, Quad with up to 4.5A Output and Factory programmed LDOs, QFN 56 | 1.35 | -40 to 105 | Industrial |