Kinetis® K60-100 MHz, Mixed-Signal Integration Microcontrollers based on Arm® Cortex®-M4 Core

Click over video to play

Product Details

Select a section:

Block Diagram

Kinetis K6x MCU Family Block Diagram

Kinetis K6x MCU Family Block Diagram

Features

Ultra-Low-Power

  • 10 low-power modes with power and clock gating for optimal peripheral activity and recovery times. Stop currents down to 2 µA, and run currents of <350 µA/MHz, with 4 µs wake-up from Stop mode
  • Full memory and analog operation down to 1.71 volts for extended battery life
  • Low-leakage wake-up unit with up to eight internal modules and 16 pins as wake-up sources in low-leakage stop (LLS)/very low-leakage stop (VLLS) modes
  • Low-power timer for continuous system operation in reduced power state

Flash, SRAM and FlexMemory

  • 256 KB - 512 KB flash. Fast access, high reliability with four-level security protection
  • 64 KB-128 KB of SRAM
  • FlexMemory: 32 bytes-4KB of user-segmentable byte write/erase EEPROM for data tables/system data. EEPROM with over 10M cycles and flash with 70 µsec write time (brownouts without data loss/corruption). No user or system intervention to complete programming and erase functions and full operation down to 1.71 volts. In addition, up to 256 KB can be used for extra program code, data or EEPROM backup

Mixed-Signal Capability

  • Two high-speed 16-bit analog-to-digital-converter (ADC) with configurable resolution. Single or differential output mode operation for improved noise rejection. 863 ns conversion time achievable with programmable delay block triggering
  • Up two 12-bit digital-to-analog-converter (DAC) for analog waveform generation for audio applications
  • Three high-speed comparators providing fast and accurate motor over-current protection by driving PWMs to a safe state
  • Analog voltage reference provides an accurate reference to analog blocks, ADC and DAC, and replaces external voltage references to reduce system cost

Performance

  • Cortex-M4 core with DSP, 100MHz clock, single-cycle MAC, and single instruction multiple data (SIMD) extensions
  • 16-channel DMA for peripheral and memory servicing with reduced CPU loading and faster system throughput
  • Crossbar switch enables concurrent multi-leader bus accesses, increasing bus bandwidth
  • Independent flash banks allow concurrent code execution and firmware updating with no performance degradation or complex coding routines

Timing and Control

  • Up to three FlexTimers with a total of 12 channels. Hardware dead-time insertion and quadrature decoding for motor control
  • Four-channel 32-bit periodic interrupt timer provides a time base for RTOS task scheduler or trigger source for ADC conversion and programmable delay block

Human-Machine Interface

  • Hardware touch-sensing interface with up to 16 inputs. Operates in all low power modes (minimum current adder when enabled). Hardware implementation avoids software polling method. High sensitivity level allows the use of overlay surfaces up to 5 mm thick

Connectivity and Communications

  • IEEE 1588 Ethernet MAC with hardware time stamping provides precision clock synchronization for real-time industrial control
  • USB 2.0 On-The-Go (full speed). Device charge detect optimizes charging current/time for portable USB devices enabling longer battery life. Low-voltage regulator supplies up to 120 mA off-chip at 3.3 volts to power external components from 5 volts input
  • Up to five UARTs with IrDA support including one UART with ISO7816 smart card support. Variety of data size, format and transmission/reception settings supported by multiple industrial communication protocols
  • Inter-IC Sound (I2S) serial interface for audio system interfacing
  • Two CAN modules for industrial network bridging
  • Three DSPI and two I2C

Reliability, Safety and Security

  • Hardware Encryption coprocessor for secure data transfer and storage. Faster than software implementations and with minimal CPU loading. Supports a wide variety of algorithms - DES, 3DES, AES, MD5, SHA-1, SHA-256
  • Memory protection unit provides memory protection for all leaders on the crossbar switch, increasing software reliability
  • Cyclic redundancy check engine validates memory contents and communication data, increasing system reliability
  • Independent-clocked COP guards against clock skew or code runaway for fail-safe applications such as the IEC 60730 safety standard for household appliances
  • External watchdog monitor drives output pin to safe state external components if watchdog event occurs
  • This product is included in NXP®.s product longevity program, with assured supply for a minimum of 10 years after launch

External Peripheral Support

  • FlexBus external bus interface provides interface options to memories and peripherals such as graphics displays. Supports up to 6 chip selects and 2GB addressable space
  • Secure digital host controller supports SD, SDIO, MMC or CE-ATA cards for in-application software upgrades, media files or adding Wi-Fi support

MCUXpresso Software and Tools

Design Resources

Documentation

Quick reference to our documentation types.

1-5 of 111 documents

Show All

Design Files

2 design files

Hardware

1-5 of 15 hardware offerings

Show All

Software

1-5 of 24 software files

Show All

Note: For better experience, software downloads are recommended on desktop.

Engineering Services

1-5 of 22 engineering services

Show All

To find a complete list of our partners that support this product, please see our Partner Marketplace.

Training

5 trainings